component
DRV8874QPWPRQ1
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Texas Instruments Brushed DC Motor Drivers, HTSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8874QPWPRQ1
Texas Instruments · Brushed DC Motor Drivers · HTSSOP-16
DRV8874QPWPRQ1 from Texas Instruments, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/IN1 | input | H-bridge control input (EN in PH/EN mode, IN1 in PWM and independent half-bridge modes), logic-level with an internal pull-down to GND; 0 to 5.5 V recommended range. |
| 2 | PH/IN2 | input | H-bridge control input (PH in PH/EN mode, IN2 in PWM and independent half-bridge modes) with an internal pull-down to GND; 0 to 5.5 V recommended range. |
| 3 | nSLEEP | input | Sleep-mode input: logic high enables the device and logic low enters low-power sleep, with an internal pull-down to GND. |
| 4 | nFAULT | output | Open-drain fault indicator, pulled low during fault conditions; requires an external pull-up resistor (IOD up to 5 mA, VOD up to 5.5 V). |
| 5 | VREF | power_in | External reference voltage input that sets the internal current-regulation limit; the recommended range is 0 to 3.6 V. |
| 6 | IPROPI | output | Analog current output proportional to the low-side MOSFET load current (AIPROPI 450 µA/A), converted to a voltage with an external resistor to GND; up to 3 mA output current. |
| 7 | IMODE | input | Four-level input that selects the current-chopping scheme (fixed off-time or cycle-by-cycle) and the overcurrent response (auto-retry or latched shutdown), set by a resistor to GND or left floating. |
| 8 | OUT1 | output | H-bridge output connected to the motor or other load, rated up to 6 A peak output current. |
| 9 | PGND | power_in | Device power ground, to be connected to the system ground. |
| 10 | OUT2 | output | H-bridge output connected to the motor or other load, rated up to 6 A peak output current. |
| 11 | VM | power_in | Power supply input of 4.5 V to 37 V (absolute maximum 40 V), to be bypassed with a 0.1 µF capacitor to GND plus a bulk capacitor rated for VM. |
| 12 | VCP | power_out | Charge pump output, connected to VM through a 100 nF, 16 V X5R or X7R ceramic capacitor. |
| 13 | CPH | passive | Charge pump switch node, connected to CPL through a 22 nF X5R or X7R ceramic capacitor rated for VM. |
| 14 | CPL | passive | Charge pump low-side pin, connected to CPH through a 22 nF X5R or X7R ceramic capacitor rated for VM (absolute maximum VVM + 0.3 V). |
| 15 | GND | power_in | Device ground, to be connected to the system ground. |
| 16 | PMODE | input | Three-level input that selects the control mode (PH/EN with logic low, PWM with logic high, independent half-bridge with high-impedance), latched at power-up or when re-enabled via nSLEEP. |
| 17 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-16 |
| Category | Motor Driver ICs |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage VM | VM | -0.3 | 40 | V | 4 | ||
| Voltage difference between GND and PGND pins | -0.3 | 0.3 | V | 4 | |||
| Charge pump low-side pin voltage CPL | -0.3 | V | 4 | ||||
| Logic pin voltage EN/IN1, IMODE, nSLEEP, PH/IN2, PMODE | -0.3 | 5.75 | V | 4 | |||
| Open-drain output pin voltage nFAULT | -0.3 | 5.75 | V | 4 | |||
| H-bridge output pin voltage OUT1, OUT2 | -0.9 | V | 4 | ||||
| Current-sense proportional output pin voltage IPROPI | -0.3 | 5.75 | V | 4 | |||
| Current-sense proportional output pin voltage IPROPI (second rating line) | -0.3 | V | 4 | ||||
| Reference input pin voltage VREF | -0.3 | 5.75 | V | 4 | |||
| Ambient temperature TA | TA | -40 | 125 | °C | 4 | ||
| Junction temperature TJ | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Supply voltage VM | VVM | 4.5 | 37 | V | 4 | ||
| Logic input voltage EN/IN1, MODE, nSLEEP, PH/IN2 | VIN | 0 | 5.5 | V | 4 | ||
| PWM frequency EN/IN1, PH/IN2 | fPWM | 0 | 100 | kHz | 4 | ||
| Open-drain pull-up voltage nFAULT | VOD | 0 | 5.5 | V | 4 | ||
| Open-drain output current nFAULT | IOD | 0 | 5 | mA | 4 | ||
| Peak output current OUT1, OUT2 | IOUT | 0 | 6 | A | Must follow power dissipation and thermal limits | 4 | |
| Current-sense output current IPROPI | IIPROPI | 0 | 3 | mA | 4 | ||
| Current-limit reference voltage VREF | VVREF | 0 | 3.6 | V | 4 | ||
| Operating ambient temperature TA | TA | -40 | 125 | °C | 4 | ||
| Operating junction temperature TJ | TJ | -40 | 150 | °C | 4 | ||
| VM sleep mode current | IVMQ | 0.75 | 1 | µA | VVM = 13.5V, nSLEEP = 0V, TJ = 25°C | 5 | |
| VM active mode current | IVM | 3 | 7 | mA | VVM = 13.5V, nSLEEP = 5V, EN/IN1 = PH/IN2 = 0V | 5 | |
| Input logic low voltage | VIL | 0 | 0.7 | V | VVM < 5V | 5 | |
| Input logic low voltage | VIL | 0 | 0.8 | V | VVM ≥ 5V | 5 | |
| Input logic high voltage | VIH | 1.5 | 5.5 | V | 5 | ||
| Input logic low current | IIL | -5 | 5 | µA | VI = 0V | 5 | |
| Input logic high current | IIH | 50 | 75 | µA | VI = 5V | 5 | |
| Three-level input logic low voltage PMODE | VTIL | 0 | 0.65 | V | 5 | ||
| Three-level input high-impedance voltage PMODE | VTIZ | 0.9 | 1 | 1.1 | V | 4.5 V < VVM < 5.5 V | 5 |
| Three-level input high-impedance voltage PMODE | VTIZ | 0.9 | 1.1 | 1.2 | V | 5.5V ≤ VVM ≤ 37V | 5 |
| Three-level input logic high voltage PMODE | VTIH | 1.5 | 5.5 | V | 5 | ||
| Three-level input logic low current PMODE | ITIL | -50 | -32 | µA | VI = 0V | 5 | |
| Three-level input high-impedance current PMODE | ITIZ | -10 | 10 | µA | VI = 1.1V | 5 | |
| Three-level input logic high current PMODE | ITIH | 113 | 150 | µA | VI = 5V | 5 | |
| Four-level input level 2 resistance to GND | RQI2 | 18.6 | 20 | 21.4 | kΩ | Resistance to GND to set four-level 2 | 5 |
| Four-level input level 1 voltage | VQI2 | 0 | 0.45 | V | Voltage to set four-level 1 | 5 | |
| Four-level input level 3 resistance to GND | RQI3 | 57.6 | 62 | 66.4 | kΩ | Resistance to GND to set four-level 3 | 6 |
| Four-level input level 4 voltage | VQI4 | 2.5 | 5.5 | V | Voltage to set four-level 4 | 6 | |
| nFAULT output logic high leakage current | IOZ | -2 | 2 | µA | VOD = 5V | 6 | |
| nFAULT output logic low voltage | VOL | 0.3 | V | IOD = 5mA | 6 | ||
| High-side MOSFET on-resistance | RDS(on)_HS | 100 | 120 | mΩ | VVM = 13.5V, IO = 2A, TJ = 25°C | 6 | |
| High-side MOSFET on-resistance | RDS(on)_HS | 160 | 190 | mΩ | VVM = 13.5V, IO = 2A, TJ = 150°C | 6 | |
| Low-side MOSFET on-resistance | RDS(on)_LS | 100 | 120 | mΩ | VVM = 13.5V, IO = -2A, TJ = 25°C | 6 | |
| Low-side MOSFET on-resistance | RDS(on)_LS | 160 | 190 | mΩ | VVM = 13.5V, IO = -2A, TJ = 150°C | 6 | |
| Current mirror proportional error (offset dominated) | AERR | -30 | 30 | mA | IOUT < 0.4A, 5.5V ≤ VVM ≤ 37V | 6 | |
| Current mirror proportional error | AERR | -7.5 | 7.5 | % | 0.4A ≤ IOUT < 1A, 5.5V ≤ VVM ≤ 37V | 6 | |
| Current mirror proportional error | AERR | -6 | 6 | % | 1A ≤ IOUT < 2A, 5.5V ≤ VVM ≤ 37V | 6 | |
| Current mirror proportional error | AERR | -5.5 | 5.5 | % | 2A ≤ IOUT ≤ 4A, 5.5V ≤ VVM ≤ 37V | 6 | |
| Supply undervoltage lockout rising threshold | VUVLO | 4.3 | 4.45 | 4.6 | V | VVM rising | 6 |
| Supply undervoltage lockout falling threshold | VUVLO | 4.2 | 4.35 | 4.5 | V | VVM falling | 6 |
| Overcurrent protection trip point | IOCP | 6 | 10 | A | 6 | ||
| Thermal shutdown temperature | TTSD | 160 | 175 | 190 | °C | 6 | |
| Junction-to-ambient thermal resistance | RθJA | 36 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 27.3 | °C/W | 5 | |||
| Junction-to-board thermal resistance | RθJB | 11.1 | °C/W | 5 | |||
| Junction-to-top characterization parameter | ΨJT | 0.4 | °C/W | 5 | |||
| Junction-to-board characterization parameter | ΨJB | 11 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 2.7 | °C/W | 5 |
CAD (KiCad official)
- Symbol:
DRV8874QPWPRQ1 - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: HTSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
drv8874qpwprq1-etched.step/drv8874qpwprq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8874qpwprq1.step/drv8874qpwprq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (42 pp, sha256
8fb256912e8d9d28, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).