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docs drv8837cdsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers drv8837cdsgr: viewers · Ray
drv8837cdsgr-etched.fit.json drv8837cdsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8837cdsgr-etched.glb drv8837cdsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8837cdsgr-etched.step drv8837cdsgr: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
drv8837cdsgr.glb Publish 0.1.0 · Ray
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page.json drv8837cdsgr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md drv8837cdsgr: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

DRV8837CDSGR

Texas Instruments · Brushed DC Motor Drivers · WSON-8-EP(2x2)

DRV8837CDSGR from Texas Instruments, in a WSON-8-EP(2x2). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Motor power supply, 0 V to 11 V. Bypass to GND with a 0.1-µF ceramic capacitor rated for VM.
2 OUT1 output H-bridge motor output 1. Connect to one terminal of the motor winding. Peak drive current 1 A; HS+LS RDS(on) typ 1 Ω.
3 OUT2 output H-bridge motor output 2. Connect to the other terminal of the motor winding. Peak drive current 1 A; HS+LS RDS(on) typ 1 Ω.
4 GND power_in Device ground. Must be connected to the PCB ground. Tie to the exposed thermal pad (PPAD) as well.
5 IN2 input PWM bridge control input 2 (IN/IN interface). Drives OUT2. Logic-level input; VIH ≥ 0.5×VCC, VIL ≤ 0.25×VCC; internal ~100-kΩ pulldown to GND.
6 IN1 input PWM bridge control input 1 (IN/IN interface). Drives OUT1. Logic-level input; VIH ≥ 0.5×VCC, VIL ≤ 0.25×VCC; internal ~100-kΩ pulldown to GND.
7 nSLEEP input Active-low sleep mode input. Logic low puts the device in low-power sleep (IVMQ ≈ 30 nA, IVCCQ ≈ 5 nA). Logic high enables normal operation. Internal ~100-kΩ pulldown to GND; wake time ≈ 30 µs.
8 VCC power_in Logic power supply, 1.8 V to 5.5 V (abs max 7 V). Bypass to GND with a 0.1-µF ceramic capacitor rated for VCC. UVLO trips at ~1.7 V falling / 1.8 V rising.
9 PPAD passive Exposed thermal pad on package underside. Solder to the PCB ground plane for proper thermal dissipation; electrically tie to GND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WSON-8-EP(2x2)
Category Motor Driver ICs
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • DRV8837CDSGR

CAD (KiCad official)

  • Symbol: DRV8837CDSGR
  • Footprint: Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
  • 3D model: WSON-8-EP(2x2) (KiCad packages3D, STEP)
  • 3D model files: drv8837cdsgr-etched.step / drv8837cdsgr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8837cdsgr.step / drv8837cdsgr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (23 pp, sha256 b4222aee632002a4, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF