component

DRV8770RGER

Public Made by Adom

by adom

Texas Instruments Gate Drivers, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsdrv8770rgerfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers drv8770rger: viewers · Ray 8d ago
drv8770rger-etched.glb Publish 0.1.0 · Ray 8d ago
drv8770rger-etched.step drv8770rger: factory component page (tier=lcsc) · Ray 8d ago
drv8770rger-hero.glb drv8770rger: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
drv8770rger-hero.overlay.json Publish 0.1.0 · Ray 8d ago
drv8770rger.glb Publish 0.1.0 · Ray 8d ago
drv8770rger.kicad_mod Publish 0.1.0 · Ray 8d ago
drv8770rger.kicad_sym Publish 0.1.0 · Ray 8d ago
drv8770rger.lbr Publish 0.1.0 · Ray 8d ago
drv8770rger.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

DRV8770RGER

Texas Instruments · Gate Drivers · VQFN-24(4x4)

DRV8770RGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INLA input Low-side gate driver control input that controls the output of the low-side gate driver.
2 INLB input Low-side gate driver control input that controls the output of the low-side gate driver.
3 RSVD2 unconnected TI reserved pin; leave floating.
4 GVDD power_in Gate driver power supply input; connect a X5R or X7R, GVDD-rated ceramic capacitor of at least 10 µF between GVDD and GND. Recommended supply range is 5 V to 20 V.
5 MODE input Mode input sets GLx polarity relative to INLx: floating gives non-inverted outputs, and connection to GVDD gives inverted outputs.
6 GND power_in Device ground.
7 NC unconnected No internal connection; can be left floating or connected to system ground.
8 NC unconnected No internal connection; can be left floating or connected to system ground.
9 RSVD3 unconnected TI reserved pin; leave floating.
10 GLB output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
11 GLA output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
12 RSVD4 input TI reserved pin; connect to GND.
13 RSVD5 unconnected TI reserved pin; leave floating.
14 RSVD6 unconnected TI reserved pin; leave floating.
15 SHB input High-side source sense input; connect to the high-side power MOSFET source.
16 GHB output High-side gate driver output; connect to the gate of the high-side power MOSFET.
17 BSTB output Bootstrap output pin; connect capacitor between BSTB and SHB.
18 SHA input High-side source sense input; connect to the high-side power MOSFET source.
19 GHA output High-side gate driver output; connect to the gate of the high-side power MOSFET.
20 BSTA output Bootstrap output pin; connect capacitor between BSTA and SHA.
21 DT input Deadtime input; connect a resistor to ground for variable deadtime, or leave floating for fixed deadtime.
22 INHA input High-side gate driver control input that controls the output of the high-side gate driver.
23 INHB input High-side gate driver control input that controls the output of the high-side gate driver.
24 RSVD1 unconnected TI reserved pin; leave floating.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Motor Driver ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Gate driver regulator pin voltage GVDD -0.3 21.5 V 5
Bootstrap pin voltage BSTx -0.3 115 V 5
Bootstrap pin voltage BSTx with respect to SHx -0.3 21.5 V 5
Logic pin voltage INHx, INLx, MODE, DT -0.3 V 5
High-side gate drive pin voltage GHx -22 115 V 5
High-side gate drive pin voltage GHx with respect to SHx -0.3 22 V 5
Transient 500-ns high-side gate drive pin voltage GHx with respect to SHx -5 22 V 5
Low-side gate drive pin voltage GLx -0.3 V 5
Transient 500-ns low-side gate drive pin voltage GLx -5 V 5
High-side source pin voltage SHx -22 100 V 5
Ambient temperature TA -40 125 °C 5
Junction temperature TJ -40 150 °C 5
Storage temperature Tstg -65 150 °C 5
Power supply voltage GVDD VGVDD 5 20 V 5
High-side source pin voltage SHx VSHx -2 85 V 5
Transient 2µs high-side source pin voltage SHx VSHx -22 85 V 5
Bootstrap pin voltage BSTx VBST 5 105 V 5
Bootstrap pin voltage BSTx with respect to SHx VBST 5 20 V 5
Logic input voltage INHx, INLx, MODE, DT VIN 0 V 5
PWM frequency INHx, INLx fPWM 0 200 kHz 5
Operating ambient temperature TA -40 125 °C 5
Operating junction temperature TJ -40 150 °C 5
GVDD standby mode current IGVDD 400 800 1400 µA INHx = INLX = 0; VBSTx = VGVDD 6
GVDD active mode current IGVDD 400 825 1400 µA INHx = INLX = Switching @20kHz; VBSTx = VGVDD; NO FETs connected 6
Bootstrap pin leakage current ILBSx 2 4 7 µA VBSTx = VSHx = 85V; VGVDD = 0V 6
Bootstrap pin active mode transient leakage current ILBS_TRAN 30 105 220 µA INHx = Switching@20kHz 6
Bootstrap pin active mode leakage static current ILBS_DC 30 85 150 µA INHx = High 6
High-side source pin leakage current ILSHx 30 55 80 µA INHx = INLX = 0; VBSTx - VSHx = 12V; VSHx = 0 to 85V 6
Input logic low voltage Mode pin VIL_MODE 0.6 V 6
Input logic low voltage INLx, INHx pins VIL 0.8 V 6
Input logic high voltage Mode pin VIH_MODE 3.7 V 6
Input logic high voltage INLx, INHx pins VIH 2 V 6
Input hysteresis Mode pin VHYS_MODE 1600 2000 2400 mV 6
Input hysteresis INLx, INHx pins VHYS 40 100 260 mV 6
INLx input logic low current (non-inverting mode) IIL_INLx -1 0 1 µA VPIN (Pin Voltage) = 0 V; INLx in non-inverting mode 6
INLx input logic low current (inverting mode) IIL_INLx 5 20 30 µA VPIN (Pin Voltage) = 0 V; INLx in inverting mode 6
INLx input logic high current (non-inverting mode) IIH_INLx 5 20 30 µA VPIN (Pin Voltage) = 5 V; INLx in non-inverting mode 6
INLx input logic high current (inverting mode) IIH_INLx 0 0.5 1.5 µA VPIN (Pin Voltage) = 5 V; INLx in inverting mode 6
INHx, MODE input logic low current IIL -1 0 1 µA VPIN (Pin Voltage) = 0 V 6
INHx, MODE input logic high current IIH 5 20 30 µA VPIN (Pin Voltage) = 5 V 6
INHx input pulldown resistance RPD_INHx 120 200 280 kΩ To GND 6
INLx input pulldown resistance RPD_INLx 120 200 280 kΩ To GND, INLx in non-inverting mode 6
INLx input pullup resistance RPU_INLx 120 200 280 kΩ To INT_5V, INLx in inverting mode 6
MODE input pulldown resistance RPD_MODE 120 200 280 kΩ To GND 6
High-side gate drive low level voltage VGHx_LO 0 0.15 0.35 V IGLx = -100 mA; VGVDD = 12V; No FETs connected 7
High-side gate drive high level voltage (VBSTx - VGHx) VGHx_HI 0.3 0.6 1.2 V IGHx = 100 mA; VGVDD = 12V; No FETs connected 7
Low-side gate drive low level voltage VGLx_LO 0 0.15 0.35 V IGLx = -100 mA; VGVDD = 12V; No FETs connected 7
Low-side gate drive high level voltage (VGVDD - VGHx) VGLx_HI 0.3 0.6 1.2 V IGHx = 100 mA; VGVDD = 12V; No FETs connected 7
High-side peak source gate current IDRIVEP_HS 400 750 1200 mA GHx-SHx = 12V 7
High-side peak sink gate current IDRIVEN_HS 850 1500 2100 mA GHx-SHx = 0V 7
Low-side peak source gate current IDRIVEP_LS 400 750 1200 mA GLx = 12V 7
Low-side peak sink gate current IDRIVEN_LS 850 1500 2100 mA GLx = 0V 7
Input to output propagation delay tPD 70 125 180 ns INHx, INLx to GHx, GLx; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx 7
Matching propagation delay per phase tPD_match -30 4 30 ns GHx turning OFF to GLx turning ON, GLx turning OFF to GHx turning ON; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx 7
Matching propagation delay phase to phase tPD_match -30 4 30 ns GHx/GLx turning ON to GHy/GLy turning ON, GHx/GLx turning OFF to GHy/GLy turning OFF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V, No load on GHx and GLx 7
GLx rise time (10% to 90%) tR_GLx 10 24 50 ns CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 7
GHx rise time (10% to 90%) tR_GHx 10 24 50 ns CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 7
GLx fall time (90% to 10%) tF_GLx 5 12 30 ns CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 7
GHx fall time (90% to 10%) tF_GHx 5 12 30 ns CLOAD = 1000 pF; VGVDD = VBSTx - VSHx > 8V; SHx = 0V 7
Gate drive dead time tDEAD 150 215 280 ns DT pin connected to GND 7

CAD (KiCad official)

  • Symbol: DRV8770RGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8770rger-etched.step / drv8770rger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8770rger.step / drv8770rger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 bdcaf87419afd7c3, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF