DRV8714SQRHARQ1

Texas Instruments · Motor Driver ICs · QFN-40-EP(6x6)

DRV8714SQRHARQ1 from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDI	input	Serial data input, data captured on the falling edge of SCLK, with internal pulldown resistor.
2	SDO	output	Serial data output, data shifted out on the rising edge of SCLK, push-pull output.
3	IN1/EN1	input	Half-bridge and H-bridge control input, with internal pulldown resistor.
4	IN2/PH1	input	Half-bridge and H-bridge control input, with internal pulldown resistor.
5	IN3/EN2	input	Half-bridge and H-bridge control input, with internal pulldown resistor.
6	IN4/PH2	input	Half-bridge and H-bridge control input, with internal pulldown resistor.
7	nSLEEP	input	Device enable pin; logic low shuts down the device and enters sleep mode, with internal pulldown resistor.
8	DRVOFF/nFLT	bidirectional	Multi-function pin used as driver shutdown input or fault indicator output, with internal pulldown resistor.
9	SO1	output	Shunt amplifier 1 output.
10	SO2	output	Shunt amplifier 2 output.
11	BRAKE	input	Power-off brake pin; logic high in low-power sleep mode enables the low-side gate drivers, with internal pulldown resistor.
12	SP1	input	Amplifier 1 positive input, connect to the positive terminal of the shunt resistor.
13	SN1	input	Amplifier 1 negative input, connect to the negative terminal of the shunt resistor.
14	SP2	input	Amplifier 2 positive input, connect to the positive terminal of the shunt resistor.
15	SN2	input	Amplifier 2 negative input, connect to the negative terminal of the shunt resistor.
16	GH1	output	High-side gate driver output for half-bridge 1, connect to the high-side MOSFET gate.
17	SH1	input	High-side source sense input for half-bridge 1, connect to the high-side MOSFET source.
18	GL1	output	Low-side gate driver output for half-bridge 1, connect to the low-side MOSFET gate.
19	PGND1	power_in	Low-side MOSFET gate drive 1-2 sense and power return, connect to system ground close to the device and half-bridges 1-2.
20	GL2	output	Low-side gate driver output for half-bridge 2, connect to the low-side MOSFET gate.
21	SH2	input	High-side source sense input for half-bridge 2, connect to the high-side MOSFET source.
22	GH2	output	High-side gate driver output for half-bridge 2, connect to the high-side MOSFET gate.
23	CP2L	passive	Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP2H and CP2L.
24	CP2H	passive	Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP2H and CP2L.
25	CP1L	passive	Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP1H and CP1L.
26	CP1H	passive	Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP1H and CP1L.
27	VCP	power_out	Charge pump output; connect a 1µF, 16V ceramic capacitor between VCP and PVDD.
28	PVDD	power_in	Driver power supply input, connect to the bridge supply with a 0.1µF ceramic capacitor rated for PVDD and a local bulk capacitor of at least 10µF to GND.
29	DRAIN	input	Bridge MOSFET drain voltage sense pin, connect to the common point of the high-side MOSFET drains.
30	GH3	output	High-side gate driver output for half-bridge 3, connect to the high-side MOSFET gate.
31	SH3	input	High-side source sense input for half-bridge 3, connect to the high-side MOSFET source.
32	GL3	output	Low-side gate driver output for half-bridge 3, connect to the low-side MOSFET gate.
33	PGND2	power_in	Low-side MOSFET gate drive 3-4 sense and power return, connect to system ground close to the device and half-bridges 3-4.
34	GL4	output	Low-side gate driver output for half-bridge 4, connect to the low-side MOSFET gate.
35	SH4	input	High-side source sense input for half-bridge 4, connect to the high-side MOSFET source.
36	GH4	output	High-side gate driver output for half-bridge 4, connect to the high-side MOSFET gate.
37	GND	power_in	Device ground, connect to system ground.
38	DVDD	power_in	Device logic and digital output supply input, also the external reference and supply for the current sense amplifier; a 1.0µF, 6.3V ceramic capacitor to GND is recommended.
39	nSCS	input	Serial chip select; a logic low enables serial interface communication, with internal pullup resistor.
40	SCLK	input	Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges, with internal pulldown resistor.
41	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	QFN-40-EP(6x6)
Category	Power Management ICs
Pins	41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Driver supply voltage	VPVDD	4.9		37	V	PVDD	23
High-side average gate drive current	IHS	0		15	mA	GHx	23
Low-side average gate drive current	ILS	0		15	mA	GLx	23
Digital supply voltage	VDVDD	3		5.5	V	DVDD	23
Digital input voltage	VDIN	0		5.5	V	BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI	23
Digital output current	IDOUT	0		5	mA	SDO	23
Open-drain pull-up voltage	VOD	0		5.5	V	DRVOFF/nFLT	23
Open-drain output current	IOD	0		5	mA	DRVOFF/nFLT	23
Brake input voltage	VBRAKE	0			V	BRAKE; max printed as PVDD	23
Amplifier reference supply voltage	VAREF	3		5.5	V	AREF	23
Shunt amplifier output current	ISO	0		5	mA	SOx	23
Operating ambient temperature	TA	-40		125	°C		23
Operating junction temperature	TJ	-40		150	°C		23
PVDD sleep mode current	IPVDDQ		2.25	3.5	µA	VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, BRAKE = 0V, -40 ≤ TJ ≤ 85°C	24
PVDD sleep mode current	IPVDDQ		10	15	µA	VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, BRAKE = 5V, -40 ≤ TJ ≤ 85°C	24
DRAIN sleep mode current	IDRAINQ		1.25	2	µA	VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C	24
DVDD sleep mode current	IDVDDQ		1.25	3	µA	VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C	24
DVDD sleep mode current	IDVDDQ		2.25	5.25	µA	VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C, DRV8714-Q1 RHA	24
PVDD active mode current	IPVDD		13.5	15.5	mA	VPVDD, VDRAIN = 13.5V, nSLEEP = 5V	24
DRAIN active mode current	IDRAIN		1	1.65	mA	VPVDD, VDRAIN = 13.5V, nSLEEP = 5V, VDS_LVL ≤ 500mV	24
DVDD active mode current	IDVDD		10	13	mA	VDVDD = 5V, SDO = 0V, DRV8714-Q1 RHA	24
Charge pump voltage vs PVDD, tripler	VVCP	9.5	10.5	11	V	Tripler mode, VPVDD ≥ 9V, IVCP ≤ 30mA	24
Charge pump voltage vs PVDD, tripler	VVCP	8.4	9	11	V	Tripler mode, VPVDD = 7V, IVCP ≤ 25mA, DRV8714-Q1 RHA	24
Charge pump voltage vs PVDD, tripler	VVCP	6.8	7.5	11	V	Tripler mode, VPVDD = 4.9V, IVCP ≤ 12mA, DRV8714-Q1 RHA	24
Charge pump voltage vs PVDD, doubler	VVCP	9.5	10.5	11	V	Doubler mode, VPVDD ≥ 13V, IVCP ≤ 25mA	24
Charge pump voltage vs PVDD, doubler	VVCP	6.9	8	11	V	Doubler mode, VPVDD = 9V, IVCP ≤ 13.5mA, DRV8714-Q1 RHA	24
Charge pump voltage vs PVDD, doubler	VVCP	5.3	6	11	V	Doubler mode, VPVDD = 7V, IVCP ≤ 10mA, DRV8714-Q1 RHA	24
Input logic low voltage, BRAKE	VIL	0		0.6	V	BRAKE	24
Input logic high voltage, BRAKE	VIH	1.8		5.5	V	BRAKE	24
Input hysteresis, BRAKE	VHYS		0.5		V	BRAKE	25
Input logic low current	IIL	-5		5	µA	VDIN = 0V, BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI	25
Input logic low current, nSCS	IIL		50	100	µA	VDIN = 0V, nSCS	25
Input logic high current	IIH		50	100	µA	VDIN = 5V, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI	25
Input logic high current, nSCS	IIH	-5		5	µA	VDIN = 5V, VDVDD = 5V, nSCS	25
Input logic high current, BRAKE	IIH		5	10	µA	VDIN = 5V, nSLEEP = 0V, BRAKE	25
Input logic high current, BRAKE	IIH		35	100	µA	VDIN = 5V, nSLEEP = 5V, BRAKE	25
Input pull-down resistance	RPD	50	100	150	kΩ	To GND, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI	25
Input pull-down resistance, BRAKE	RPD	500	1000	1500	kΩ	BRAKE to GND, nSLEEP = 0V, BRAKE ≤ 2 V, 4.9V ≤ VPVDD ≤ VPOB_OV	25
Input pull-down resistance, BRAKE	RPD	50	136	200	kΩ	BRAKE to GND, nSLEEP = 5V, BRAKE ≤ 2 V, 4.9V ≤ VPVDD ≤ VPOB_OV	25
Input pull-up resistance	RPU	50	100	150	kΩ	To DVDD, nSCS	25
Four-level input 2 resistor	RQI2	44.65	47	49.35	kΩ	GAIN, MODE; level 2 set by resistor to GND	25
Six-level input 2 resistor	RSI2	28.5	30	31.5	kΩ	IDRIVE, VDS; level 2 set by resistor to GND	25
Six-level input 3 resistor	RSI3	95	100	105	kΩ	IDRIVE, VDS; level 3 set by resistor to GND	25
Six-level input 5 resistor	RSI5	58.9	62	65.1	kΩ	IDRIVE, VDS; level 5 set by resistor to DVDD	25
Output logic low voltage	VOL			0.5	V	IDOUT = 5mA	25
Digital oscillator switching frequency	fDVDD		14.25		MHz	Main frequency of spread spectrum	24
Charge pump switching frequency	fVCP		400		kHz	Main frequency of spread spectrum	24
Junction-to-ambient thermal resistance	RθJA		31		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
Junction-to-case (top) thermal resistance	RθJC(top)		20.9		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
Junction-to-board thermal resistance	RθJB		12.5		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
Junction-to-top characterization parameter	ΨJT		0.2		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
Junction-to-board characterization parameter	ΨJB		12.4		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
Junction-to-case (bottom) thermal resistance	RθJC(bot)		2.3		°C/W	DRV8714-Q1 RHA (VQFN) 40-pin	23
ESD HBM	V(ESD)	-2000		2000	V	Human body model, AEC Q100-002, HBM ESD classification level 2	23
ESD CDM, corner pins	V(ESD)	-750		750	V	Charged device model, AEC Q100-011, class C4B, corner pins	23
ESD CDM, other pins	V(ESD)	-500		500	V	Charged device model, AEC Q100-011, class C4B, other pins	23

CAD (KiCad official)

Symbol: DRV8714SQRHARQ1
Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
3D model files: drv8714sqrharq1-etched.step / drv8714sqrharq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8714sqrharq1.step / drv8714sqrharq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (193 pp, sha256 a2520e0a5afb2156, retrieved 2026-10-23, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DRV8714SQRHARQ1

**Texas Instruments** · Motor Driver ICs · QFN-40-EP(6x6)

DRV8714SQRHARQ1 from Texas Instruments, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SDI | input | Serial data input, data captured on the falling edge of SCLK, with internal pulldown resistor. |
| 2 | SDO | output | Serial data output, data shifted out on the rising edge of SCLK, push-pull output. |
| 3 | IN1/EN1 | input | Half-bridge and H-bridge control input, with internal pulldown resistor. |
| 4 | IN2/PH1 | input | Half-bridge and H-bridge control input, with internal pulldown resistor. |
| 5 | IN3/EN2 | input | Half-bridge and H-bridge control input, with internal pulldown resistor. |
| 6 | IN4/PH2 | input | Half-bridge and H-bridge control input, with internal pulldown resistor. |
| 7 | nSLEEP | input | Device enable pin; logic low shuts down the device and enters sleep mode, with internal pulldown resistor. |
| 8 | DRVOFF/nFLT | bidirectional | Multi-function pin used as driver shutdown input or fault indicator output, with internal pulldown resistor. |
| 9 | SO1 | output | Shunt amplifier 1 output. |
| 10 | SO2 | output | Shunt amplifier 2 output. |
| 11 | BRAKE | input | Power-off brake pin; logic high in low-power sleep mode enables the low-side gate drivers, with internal pulldown resistor. |
| 12 | SP1 | input | Amplifier 1 positive input, connect to the positive terminal of the shunt resistor. |
| 13 | SN1 | input | Amplifier 1 negative input, connect to the negative terminal of the shunt resistor. |
| 14 | SP2 | input | Amplifier 2 positive input, connect to the positive terminal of the shunt resistor. |
| 15 | SN2 | input | Amplifier 2 negative input, connect to the negative terminal of the shunt resistor. |
| 16 | GH1 | output | High-side gate driver output for half-bridge 1, connect to the high-side MOSFET gate. |
| 17 | SH1 | input | High-side source sense input for half-bridge 1, connect to the high-side MOSFET source. |
| 18 | GL1 | output | Low-side gate driver output for half-bridge 1, connect to the low-side MOSFET gate. |
| 19 | PGND1 | power_in | Low-side MOSFET gate drive 1-2 sense and power return, connect to system ground close to the device and half-bridges 1-2. |
| 20 | GL2 | output | Low-side gate driver output for half-bridge 2, connect to the low-side MOSFET gate. |
| 21 | SH2 | input | High-side source sense input for half-bridge 2, connect to the high-side MOSFET source. |
| 22 | GH2 | output | High-side gate driver output for half-bridge 2, connect to the high-side MOSFET gate. |
| 23 | CP2L | passive | Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP2H and CP2L. |
| 24 | CP2H | passive | Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP2H and CP2L. |
| 25 | CP1L | passive | Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP1H and CP1L. |
| 26 | CP1H | passive | Charge pump switching node; connect a 100nF capacitor rated for PVDD between CP1H and CP1L. |
| 27 | VCP | power_out | Charge pump output; connect a 1µF, 16V ceramic capacitor between VCP and PVDD. |
| 28 | PVDD | power_in | Driver power supply input, connect to the bridge supply with a 0.1µF ceramic capacitor rated for PVDD and a local bulk capacitor of at least 10µF to GND. |
| 29 | DRAIN | input | Bridge MOSFET drain voltage sense pin, connect to the common point of the high-side MOSFET drains. |
| 30 | GH3 | output | High-side gate driver output for half-bridge 3, connect to the high-side MOSFET gate. |
| 31 | SH3 | input | High-side source sense input for half-bridge 3, connect to the high-side MOSFET source. |
| 32 | GL3 | output | Low-side gate driver output for half-bridge 3, connect to the low-side MOSFET gate. |
| 33 | PGND2 | power_in | Low-side MOSFET gate drive 3-4 sense and power return, connect to system ground close to the device and half-bridges 3-4. |
| 34 | GL4 | output | Low-side gate driver output for half-bridge 4, connect to the low-side MOSFET gate. |
| 35 | SH4 | input | High-side source sense input for half-bridge 4, connect to the high-side MOSFET source. |
| 36 | GH4 | output | High-side gate driver output for half-bridge 4, connect to the high-side MOSFET gate. |
| 37 | GND | power_in | Device ground, connect to system ground. |
| 38 | DVDD | power_in | Device logic and digital output supply input, also the external reference and supply for the current sense amplifier; a 1.0µF, 6.3V ceramic capacitor to GND is recommended. |
| 39 | nSCS | input | Serial chip select; a logic low enables serial interface communication, with internal pullup resistor. |
| 40 | SCLK | input | Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges, with internal pulldown resistor. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | QFN-40-EP(6x6) |
| Category | Power Management ICs |
| Pins | 41 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Driver supply voltage | VPVDD | 4.9 |  | 37 | V | PVDD | 23 |
| High-side average gate drive current | IHS | 0 |  | 15 | mA | GHx | 23 |
| Low-side average gate drive current | ILS | 0 |  | 15 | mA | GLx | 23 |
| Digital supply voltage | VDVDD | 3 |  | 5.5 | V | DVDD | 23 |
| Digital input voltage | VDIN | 0 |  | 5.5 | V | BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, nSCS, SCLK, SDI | 23 |
| Digital output current | IDOUT | 0 |  | 5 | mA | SDO | 23 |
| Open-drain pull-up voltage | VOD | 0 |  | 5.5 | V | DRVOFF/nFLT | 23 |
| Open-drain output current | IOD | 0 |  | 5 | mA | DRVOFF/nFLT | 23 |
| Brake input voltage | VBRAKE | 0 |  |  | V | BRAKE; max printed as PVDD | 23 |
| Amplifier reference supply voltage | VAREF | 3 |  | 5.5 | V | AREF | 23 |
| Shunt amplifier output current | ISO | 0 |  | 5 | mA | SOx | 23 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 23 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 23 |
| PVDD sleep mode current | IPVDDQ |  | 2.25 | 3.5 | µA | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, BRAKE = 0V, -40 ≤ TJ ≤ 85°C | 24 |
| PVDD sleep mode current | IPVDDQ |  | 10 | 15 | µA | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, BRAKE = 5V, -40 ≤ TJ ≤ 85°C | 24 |
| DRAIN sleep mode current | IDRAINQ |  | 1.25 | 2 | µA | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C | 24 |
| DVDD sleep mode current | IDVDDQ |  | 1.25 | 3 | µA | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C | 24 |
| DVDD sleep mode current | IDVDDQ |  | 2.25 | 5.25 | µA | VPVDD, VDRAIN = 13.5V, nSLEEP = 0V, -40 ≤ TJ ≤ 85°C, DRV8714-Q1 RHA | 24 |
| PVDD active mode current | IPVDD |  | 13.5 | 15.5 | mA | VPVDD, VDRAIN = 13.5V, nSLEEP = 5V | 24 |
| DRAIN active mode current | IDRAIN |  | 1 | 1.65 | mA | VPVDD, VDRAIN = 13.5V, nSLEEP = 5V, VDS_LVL ≤ 500mV | 24 |
| DVDD active mode current | IDVDD |  | 10 | 13 | mA | VDVDD = 5V, SDO = 0V, DRV8714-Q1 RHA | 24 |
| Charge pump voltage vs PVDD, tripler | VVCP | 9.5 | 10.5 | 11 | V | Tripler mode, VPVDD ≥ 9V, IVCP ≤ 30mA | 24 |
| Charge pump voltage vs PVDD, tripler | VVCP | 8.4 | 9 | 11 | V | Tripler mode, VPVDD = 7V, IVCP ≤ 25mA, DRV8714-Q1 RHA | 24 |
| Charge pump voltage vs PVDD, tripler | VVCP | 6.8 | 7.5 | 11 | V | Tripler mode, VPVDD = 4.9V, IVCP ≤ 12mA, DRV8714-Q1 RHA | 24 |
| Charge pump voltage vs PVDD, doubler | VVCP | 9.5 | 10.5 | 11 | V | Doubler mode, VPVDD ≥ 13V, IVCP ≤ 25mA | 24 |
| Charge pump voltage vs PVDD, doubler | VVCP | 6.9 | 8 | 11 | V | Doubler mode, VPVDD = 9V, IVCP ≤ 13.5mA, DRV8714-Q1 RHA | 24 |
| Charge pump voltage vs PVDD, doubler | VVCP | 5.3 | 6 | 11 | V | Doubler mode, VPVDD = 7V, IVCP ≤ 10mA, DRV8714-Q1 RHA | 24 |
| Input logic low voltage, BRAKE | VIL | 0 |  | 0.6 | V | BRAKE | 24 |
| Input logic high voltage, BRAKE | VIH | 1.8 |  | 5.5 | V | BRAKE | 24 |
| Input hysteresis, BRAKE | VHYS |  | 0.5 |  | V | BRAKE | 25 |
| Input logic low current | IIL | -5 |  | 5 | µA | VDIN = 0V, BRAKE, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI | 25 |
| Input logic low current, nSCS | IIL |  | 50 | 100 | µA | VDIN = 0V, nSCS | 25 |
| Input logic high current | IIH |  | 50 | 100 | µA | VDIN = 5V, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI | 25 |
| Input logic high current, nSCS | IIH | -5 |  | 5 | µA | VDIN = 5V, VDVDD = 5V, nSCS | 25 |
| Input logic high current, BRAKE | IIH |  | 5 | 10 | µA | VDIN = 5V, nSLEEP = 0V, BRAKE | 25 |
| Input logic high current, BRAKE | IIH |  | 35 | 100 | µA | VDIN = 5V, nSLEEP = 5V, BRAKE | 25 |
| Input pull-down resistance | RPD | 50 | 100 | 150 | kΩ | To GND, DRVOFF/nFLT, INx/ENx, INx/PHx, nSLEEP, SCLK, SDI | 25 |
| Input pull-down resistance, BRAKE | RPD | 500 | 1000 | 1500 | kΩ | BRAKE to GND, nSLEEP = 0V, BRAKE ≤ 2 V, 4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| Input pull-down resistance, BRAKE | RPD | 50 | 136 | 200 | kΩ | BRAKE to GND, nSLEEP = 5V, BRAKE ≤ 2 V, 4.9V ≤ VPVDD ≤ VPOB_OV | 25 |
| Input pull-up resistance | RPU | 50 | 100 | 150 | kΩ | To DVDD, nSCS | 25 |
| Four-level input 2 resistor | RQI2 | 44.65 | 47 | 49.35 | kΩ | GAIN, MODE; level 2 set by resistor to GND | 25 |
| Six-level input 2 resistor | RSI2 | 28.5 | 30 | 31.5 | kΩ | IDRIVE, VDS; level 2 set by resistor to GND | 25 |
| Six-level input 3 resistor | RSI3 | 95 | 100 | 105 | kΩ | IDRIVE, VDS; level 3 set by resistor to GND | 25 |
| Six-level input 5 resistor | RSI5 | 58.9 | 62 | 65.1 | kΩ | IDRIVE, VDS; level 5 set by resistor to DVDD | 25 |
| Output logic low voltage | VOL |  |  | 0.5 | V | IDOUT = 5mA | 25 |
| Digital oscillator switching frequency | fDVDD |  | 14.25 |  | MHz | Main frequency of spread spectrum | 24 |
| Charge pump switching frequency | fVCP |  | 400 |  | kHz | Main frequency of spread spectrum | 24 |
| Junction-to-ambient thermal resistance | RθJA |  | 31 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 20.9 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| Junction-to-board thermal resistance | RθJB |  | 12.5 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| Junction-to-top characterization parameter | ΨJT |  | 0.2 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| Junction-to-board characterization parameter | ΨJB |  | 12.4 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.3 |  | °C/W | DRV8714-Q1 RHA (VQFN) 40-pin | 23 |
| ESD HBM | V(ESD) | -2000 |  | 2000 | V | Human body model, AEC Q100-002, HBM ESD classification level 2 | 23 |
| ESD CDM, corner pins | V(ESD) | -750 |  | 750 | V | Charged device model, AEC Q100-011, class C4B, corner pins | 23 |
| ESD CDM, other pins | V(ESD) | -500 |  | 500 | V | Charged device model, AEC Q100-011, class C4B, other pins | 23 |

## CAD (KiCad official)

- Symbol: `DRV8714SQRHARQ1`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `drv8714sqrharq1-etched.step` / `drv8714sqrharq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8714sqrharq1.step` / `drv8714sqrharq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8714-q1) (193 pp, sha256 `a2520e0a5afb2156`, retrieved 2026-10-23, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8714sqrharq1-datasheet.pdf)