component

DRV8706HQRHBRQ1

Public Made by Adom

by adom

Texas Instruments Brushed DC Motor Drivers, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentmotor driver icsdrv8706hqrhbrq1factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
drv8706hqrhbrq1 / README.md
History Download
Ray Initial commit: component/drv8706hqrhbrq1 8148e05 1d ago

DRV8706HQRHBRQ1

Texas Instruments · Brushed DC Motor Drivers · VQFN-32(5x5)

DRV8706HQRHBRQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Device ground pin connected to system ground plane.
2 DVDD power_in Device logic and digital output power supply input, 3V to 5.5V, requiring 1.0 µF bypass capacitor to GND.
3 GAIN input Amplifier gain setting 4-level analog input configured by external resistors to select 10, 20, 40, or 80 V/V.
4 VDS input VDS monitor threshold setting 6-level analog input configured by external resistors to set overcurrent protection threshold.
5 IDRIVE input Gate driver output current setting 6-level analog input configured by external resistors to select drive current from 0.5 to 62 mA.
6 MODE input PWM input mode setting 4-level analog input configured by external resistors to select half-bridge, H-bridge PH/EN, H-bridge PWM, or solenoid control mode.
7 IN1/EN input Half-bridge or H-bridge control digital input with internal pull-down resistor.
8 nHIZ1 input Half-bridge control input for placing high-side and low-side driver to high impedance state with internal pull-down resistor.
9 IN2/PH input Half-bridge or phase control digital input with internal pull-down resistor.
10 nHIZ2 input Half-bridge control input for placing high-side and low-side driver to high impedance state with internal pull-down resistor.
11 nSLEEP input Device enable pin with logic low disabling drivers and entering low-power sleep mode, internal pull-down resistor.
12 DRVOFF input Driver disable control input with logic high pulling all gate driver outputs low regardless of input signals, internal pull-down resistor.
13 nFAULT tri_state Fault indicator open-drain output pulled to logic low during fault condition, requires external pull-up resistor to VCC.
14 SO output Shunt amplifier analog output with adjustable gain and output range from 0.25V to AREF - 0.25V.
15 RSVD unconnected Reserved pin that should be connected to ground or left open.
16 AREF power_in External voltage reference for current sense amplifier supply, 3V to 5.5V, requiring 0.1 µF bypass capacitor to AGND.
17 AGND power_in Analog ground return for current sense amplifier and shunt monitor inputs connected to system ground plane.
18 SP input Shunt amplifier positive input connected to positive terminal of external shunt resistor with high common-mode range.
19 SN input Shunt amplifier negative input connected to negative terminal of external shunt resistor with high common-mode range.
20 GH1 output High-side gate driver output connected to high-side MOSFET gate of bridge half 1 with adjustable drive current.
21 SH1 input High-side source sense input connected to source node of high-side MOSFET in half-bridge 1 for VDS and VGS monitoring.
22 GL1 output Low-side gate driver output connected to low-side MOSFET gate of bridge half 1 with adjustable drive current.
23 SL1 input Low-side source sense and power return input of half-bridge 1 connected via low impedance path to low-side MOSFET ground.
24 SL2 input Low-side source sense and power return input of half-bridge 2 connected via low impedance path to low-side MOSFET ground.
25 GL2 output Low-side gate driver output connected to low-side MOSFET gate of bridge half 2 with adjustable drive current.
26 SH2 input High-side source sense input connected to source node of high-side MOSFET in half-bridge 2 for VDS and VGS monitoring.
27 GH2 output High-side gate driver output connected to high-side MOSFET gate of bridge half 2 with adjustable drive current.
28 DRAIN input Bridge MOSFET drain voltage sense input connected to common drain point of high-side MOSFETs for VDS monitoring.
29 PVDD power_in Device driver power supply input operating 4.9V to 37V maximum, requiring 0.1 µF and ≥10 µF bulk capacitor bypass to GND.
30 VCP power_out Charge pump voltage output regulating 4.5V to 11V relative to PVDD to supply high-side gate driver.
31 CPH bidirectional Charge pump high-side switching node requiring 0.1 µF capacitor between CPH and CPL for pump operation.
32 CPL bidirectional Charge pump low-side switching node requiring 0.1 µF capacitor between CPH and CPL for pump operation.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32(5x5)
Category Motor Driver ICs
Pins 33

CAD (KiCad official)

  • Symbol: DRV8706HQRHBRQ1
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
  • 3D model files: drv8706hqrhbrq1-etched.step / drv8706hqrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8706hqrhbrq1.step / drv8706hqrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 edef015b972ba63d, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF