component
DRV8703QRHBTQ1
Public Made by Adomby adom
Texas Instruments Brushed DC Motor Drivers, VQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8703QRHBTQ1
Texas Instruments · Brushed DC Motor Drivers · VQFN-32(5x5)
DRV8703QRHBTQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground that must be connected to the system ground. |
| 2 | IN1/PH | input | Input control pin whose logic function depends on the MODE pin and which has an internal pulldown resistor. |
| 3 | IN2/EN | input | Input control pin whose logic function depends on the MODE pin and which has an internal pulldown resistor. |
| 4 | SDO | output | SPI output that is an open-drain output requiring an external pullup resistor. |
| 5 | nSCS | input | SPI chip select and enable, active low. |
| 6 | SDI | input | SPI input signal with an internal pulldown resistor. |
| 7 | SCLK | input | SPI clock signal with an internal pulldown resistor. |
| 8 | nSLEEP | input | Pull to logic low to put the device into low-power sleep mode with the FETs in Hi-Z; has an internal pulldown resistor. |
| 9 | nWDFLT | output | Watchdog fault indication pin that is pulled logic low on a watchdog fault and requires an external pullup resistor (open-drain). |
| 10 | nFAULT | output | Fault indication open-drain output that is pulled logic low when a fault condition occurs and requires an external pullup resistor. |
| 11 | MODE | input | Control interface select pin latched on power-up or exit from sleep: logic low for PH/EN, high for independent half-bridge, Hi-Z for PWM. |
| 12 | DVDD | power_out | Logic regulator output for the 3.3V logic supply, to be bypassed to ground with a 6.3V, 1µF ceramic capacitor. |
| 13 | GND | power_in | Device ground that must be connected to the system ground. |
| 14 | AVDD | power_out | 5V analog supply regulator output, to be bypassed to ground with a 6.3V, 1µF ceramic capacitor. |
| 15 | VREF | power_in | Current set reference input whose voltage sets the chopping current; valid range is 0.3 V to 3.6 V. |
| 16 | SO | output | Shunt-amplifier output equal to SP voltage times AV plus offset, with no more than 1 nF of capacitance allowed on this pin. |
| 17 | GND | power_in | Device ground that must be connected to the system ground. |
| 18 | GH1 | output | High-side gate drive output that connects to the high-side FET gate. |
| 19 | SH1 | input | High-side source connection that must be connected to the high-side FET source. |
| 20 | GL1 | output | Low-side gate drive output that connects to the low-side FET gate. |
| 21 | SP | input | Shunt-amplifier positive input that connects to the current-sense resistor. |
| 22 | SN | input | Shunt-amplifier negative input that connects to the current-sense resistor. |
| 23 | SL2 | input | Low-side source connection that must be connected to the low-side FET source. |
| 24 | GL2 | output | Low-side gate drive output that connects to the low-side FET gate. |
| 25 | SH2 | input | High-side source connection that must be connected to the high-side FET source. |
| 26 | GH2 | output | High-side gate drive output that connects to the high-side FET gate. |
| 27 | VDRAIN | input | High-side FET drain connection that is common to the two H-bridges. |
| 28 | VM | power_in | Motor supply input that is bypassed with a 0.1µF ceramic plus a 10µF (minimum) capacitor. |
| 29 | VCP | power_out | Charge-pump output that connects to VM through a 16V, 1µF ceramic capacitor. |
| 30 | CPH | passive | Charge-pump switching node that connects to CPL through a 0.1µF X7R capacitor rated for the supply voltage (VM). |
| 31 | CPL | passive | Charge-pump switching node that connects to CPH through a 0.1µF X7R capacitor rated for the supply voltage (VM). |
| 32 | NC | unconnected | No connect pin with no internal connection. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Motor Driver ICs |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VM | -0.3 | 47 | V | 6 | ||
| Internal logic regulator voltage | DVDD | -0.3 | 3.8 | V | 6 | ||
| Internal analog regulator voltage | AVDD | -0.3 | 5.75 | V | 6 | ||
| Drain pin voltage | VDRAIN | -0.3 | 47 | V | 6 | ||
| Voltage difference between supply and VDRAIN | VM - VDRAIN | -10 | 10 | V | 6 | ||
| Control pin voltage | -0.3 | 5.75 | V | IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, VDS, MODE, nSCS, SCLK, SDI, SDO, nWDFLT | 6 | ||
| Shunt amplifier output pin voltage | SO | -0.3 | 5.75 | V | 6 | ||
| Shunt amplifier output pin current | SO | 0 | 5 | mA | 6 | ||
| Open-drain output current | 0 | 10 | mA | nFAULT, SDO, nWDFLT | 6 | ||
| Gate pin source current | 0 | 250 | mA | GH1, GL1, GH2, GL2 | 6 | ||
| Gate pin sink current | 0 | 500 | mA | GH1, GL1, GH2, GL2 | 6 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 6 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 6 | ||
| Power supply voltage | VVM | 5.5 | 45 | V | 7 | ||
| Current Shunt Amplifier Reference Voltage | VVREF | 0.3 | 3.6 | V | 7 | ||
| Applied PWM signal (IN1/IN2) | f(PWM) | 100 | kHz | 7 | |||
| AVDD external load current | IAVDD | 30 | mA | 7 | |||
| DVDD external load current | IDVDD | 30 | mA | 7 | |||
| Shunt-amplifier output-current loading | ISO | 5 | mA | 7 | |||
| Operating ambient temperature | TA | -40 | 125 | °C | 7 | ||
| VM operating voltage | VVM | 5.5 | 45 | V | Gate drivers functional | 7 | |
| VM operating voltage | VVM | 4.5 | 45 | V | Logic functional | 7 | |
| VM operating supply current | IVM | 5.5 | 7.5 | 12 | mA | VVM = 13.5 V; nSLEEP=1 | 7 |
| Internal logic regulator voltage | VDVDD | 3 | 3.3 | 3.5 | V | 2-mA load | 7 |
| Internal logic regulator voltage | VDVDD | 2.9 | 3.2 | 3.5 | V | 30-mA load, VVM = 13.5 V | 7 |
| Internal logic regulator voltage | VAVDD | 4.7 | 5 | 5.3 | V | 2-mA load | 7 |
| Internal logic regulator voltage | VAVDD | 4.6 | 5 | 5.3 | V | 30-mA load, VVM = 13.5 V | 7 |
| VCP operating voltage | VVCP | 22.5 | 23.5 | 24.5 | V | VVM = 13.5 V; IVCP = 0 to 12 mA | 7 |
| VCP operating voltage | VVCP | 13.7 | 14 | 14.8 | V | VVM = 8 V; IVCP = 0 to 10 mA | 7 |
| VCP operating voltage | VVCP | 8.9 | 9.1 | 9.5 | V | VVM = 5.5 V; IVCP = 0 to 8 mA | 7 |
| Input logic-low voltage | VIL | 0 | 0.8 | V | 8 | ||
| Input logic-high voltage | VIH | 1.5 | 5.25 | V | 8 | ||
| Input logic-low current | IIL | -5 | 5 | µA | VIN = 0 V | 8 | |
| Pulldown resistance | RPD | 64 | 100 | 173 | kΩ | IN1/PH, IN2/EN, nSLEEP, nSCS, SCLK, SDI | 8 |
| Output logic-low voltage | VOL | 0.1 | V | IO = 2 mA | 8 | ||
| High-side VGS gate drive (gate-to-source) | VGSH | 10.5 | 11.5 | V | VVM > 13.5 V; VGSH with respect to SHx | 8 | |
| High-side VGS gate drive (gate-to-source) | VGSH | 5.7 | 6.8 | V | VVM = 8 V; VGSH with respect to SHx | 8 | |
| High-side VGS gate drive (gate-to-source) | VGSH | 3.4 | 4 | V | VVM = 5.5 V; VGSH with respect to SHx | 8 | |
| Gate-drive clamping voltage positive | VC(GS) | 16.3 | 17 | 17.8 | V | Positive clamping voltage | 12 |
| Gate-drive clamping voltage negative | VC(GS) | -1 | -0.7 | -0.5 | V | Negative clamping voltage | 12 |
| Amplifier gain (DRV8703-Q1) | AV | 9.75 | 10 | 10.25 | V/V | GAIN_CS = 00; 10 < VSP < 450 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 19.3 | 19.8 | 20.3 | V/V | GAIN_CS = 01; 60 < VSP < 225 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 38.4 | 39.4 | 40.4 | V/V | GAIN_CS = 10; 10 < VSP < 112 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 73 | 78 | 81 | V/V | GAIN_CS = 11; 10 < VSP < 56 mV; VSN = GND | 11 |
| VM undervoltage lockout (falling) | V(UVLO2) | 5.25 | 5.45 | V | VM falling; UVLO2 report | 11 | |
| VM undervoltage lockout (rising) | V(UVLO2) | 5.4 | 5.65 | V | VM rising; UVLO2 recovery | 11 | |
| Overcurrent protection trip level, measured by sense amplifier | VSP(OCP) | 0.8 | 1 | 1.2 | V | VSP with respect to GND | 11 |
| Thermal warning temperature | T(OTW) | 120 | 135 | 145 | °C | Die temperature TJ | 11 |
| Charge-pump switching frequency | fS(VCP) | 200 | 400 | 700 | kHz | VM > UVLO2 | 12 |
| Overcurrent deglitch time | t(OCP) | 3.7 | 4 | 4.3 | µs | 13 | |
| Overcurrent retry time | t(RETRY) | 2.8 | 3 | 3.2 | ms | 13 | |
| Minimum SPI clock period | t(CLK) | 100 | ns | 12 | |||
| SDI input data setup time | t(SU_SDI) | 20 | ns | 12 | |||
| SDI input data hold time | t(HD_SDI) | 30 | ns | 12 | |||
| Junction-to-ambient thermal resistance | RθJA | 32.9 | °C/W | 7 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 19.6 | °C/W | 7 | |||
| Junction-to-board thermal resistance | RθJB | 6.8 | °C/W | 7 | |||
| Junction-to-top characterization parameter | ψJT | 0.3 | °C/W | 7 | |||
| Junction-to-board characterization parameter | ψJB | 6.8 | °C/W | 7 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 1.8 | °C/W | 7 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | SL2 23 23 I Low-side source. Connect this pin to the low-side FET source. SN 22 22 I Shunt-amplifier negative input. Connect this pin to the current-sense resistor. | 5 |
CAD (KiCad official)
- Symbol:
DRV8703QRHBTQ1 - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
drv8703qrhbtq1-etched.step/drv8703qrhbtq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8703qrhbtq1.step/drv8703qrhbtq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (63 pp, sha256
41f247d459b34028, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8703QRHBTQ1
**Texas Instruments** · Brushed DC Motor Drivers · VQFN-32(5x5)
DRV8703QRHBTQ1 from Texas Instruments, in a VQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device ground that must be connected to the system ground. |
| 2 | IN1/PH | input | Input control pin whose logic function depends on the MODE pin and which has an internal pulldown resistor. |
| 3 | IN2/EN | input | Input control pin whose logic function depends on the MODE pin and which has an internal pulldown resistor. |
| 4 | SDO | output | SPI output that is an open-drain output requiring an external pullup resistor. |
| 5 | nSCS | input | SPI chip select and enable, active low. |
| 6 | SDI | input | SPI input signal with an internal pulldown resistor. |
| 7 | SCLK | input | SPI clock signal with an internal pulldown resistor. |
| 8 | nSLEEP | input | Pull to logic low to put the device into low-power sleep mode with the FETs in Hi-Z; has an internal pulldown resistor. |
| 9 | nWDFLT | output | Watchdog fault indication pin that is pulled logic low on a watchdog fault and requires an external pullup resistor (open-drain). |
| 10 | nFAULT | output | Fault indication open-drain output that is pulled logic low when a fault condition occurs and requires an external pullup resistor. |
| 11 | MODE | input | Control interface select pin latched on power-up or exit from sleep: logic low for PH/EN, high for independent half-bridge, Hi-Z for PWM. |
| 12 | DVDD | power_out | Logic regulator output for the 3.3V logic supply, to be bypassed to ground with a 6.3V, 1µF ceramic capacitor. |
| 13 | GND | power_in | Device ground that must be connected to the system ground. |
| 14 | AVDD | power_out | 5V analog supply regulator output, to be bypassed to ground with a 6.3V, 1µF ceramic capacitor. |
| 15 | VREF | power_in | Current set reference input whose voltage sets the chopping current; valid range is 0.3 V to 3.6 V. |
| 16 | SO | output | Shunt-amplifier output equal to SP voltage times AV plus offset, with no more than 1 nF of capacitance allowed on this pin. |
| 17 | GND | power_in | Device ground that must be connected to the system ground. |
| 18 | GH1 | output | High-side gate drive output that connects to the high-side FET gate. |
| 19 | SH1 | input | High-side source connection that must be connected to the high-side FET source. |
| 20 | GL1 | output | Low-side gate drive output that connects to the low-side FET gate. |
| 21 | SP | input | Shunt-amplifier positive input that connects to the current-sense resistor. |
| 22 | SN | input | Shunt-amplifier negative input that connects to the current-sense resistor. |
| 23 | SL2 | input | Low-side source connection that must be connected to the low-side FET source. |
| 24 | GL2 | output | Low-side gate drive output that connects to the low-side FET gate. |
| 25 | SH2 | input | High-side source connection that must be connected to the high-side FET source. |
| 26 | GH2 | output | High-side gate drive output that connects to the high-side FET gate. |
| 27 | VDRAIN | input | High-side FET drain connection that is common to the two H-bridges. |
| 28 | VM | power_in | Motor supply input that is bypassed with a 0.1µF ceramic plus a 10µF (minimum) capacitor. |
| 29 | VCP | power_out | Charge-pump output that connects to VM through a 16V, 1µF ceramic capacitor. |
| 30 | CPH | passive | Charge-pump switching node that connects to CPL through a 0.1µF X7R capacitor rated for the supply voltage (VM). |
| 31 | CPL | passive | Charge-pump switching node that connects to CPH through a 0.1µF X7R capacitor rated for the supply voltage (VM). |
| 32 | NC | unconnected | No connect pin with no internal connection. |
| 33 | PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32(5x5) |
| Category | Motor Driver ICs |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VM | -0.3 | | 47 | V | | 6 |
| Internal logic regulator voltage | DVDD | -0.3 | | 3.8 | V | | 6 |
| Internal analog regulator voltage | AVDD | -0.3 | | 5.75 | V | | 6 |
| Drain pin voltage | VDRAIN | -0.3 | | 47 | V | | 6 |
| Voltage difference between supply and VDRAIN | VM - VDRAIN | -10 | | 10 | V | | 6 |
| Control pin voltage | | -0.3 | | 5.75 | V | IN1, IN2, nSLEEP, nFAULT, VREF, IDRIVE, VDS, MODE, nSCS, SCLK, SDI, SDO, nWDFLT | 6 |
| Shunt amplifier output pin voltage | SO | -0.3 | | 5.75 | V | | 6 |
| Shunt amplifier output pin current | SO | 0 | | 5 | mA | | 6 |
| Open-drain output current | | 0 | | 10 | mA | nFAULT, SDO, nWDFLT | 6 |
| Gate pin source current | | 0 | | 250 | mA | GH1, GL1, GH2, GL2 | 6 |
| Gate pin sink current | | 0 | | 500 | mA | GH1, GL1, GH2, GL2 | 6 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 6 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 6 |
| Power supply voltage | VVM | 5.5 | | 45 | V | | 7 |
| Current Shunt Amplifier Reference Voltage | VVREF | 0.3 | | 3.6 | V | | 7 |
| Applied PWM signal (IN1/IN2) | f(PWM) | | | 100 | kHz | | 7 |
| AVDD external load current | IAVDD | | | 30 | mA | | 7 |
| DVDD external load current | IDVDD | | | 30 | mA | | 7 |
| Shunt-amplifier output-current loading | ISO | | | 5 | mA | | 7 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 7 |
| VM operating voltage | VVM | 5.5 | | 45 | V | Gate drivers functional | 7 |
| VM operating voltage | VVM | 4.5 | | 45 | V | Logic functional | 7 |
| VM operating supply current | IVM | 5.5 | 7.5 | 12 | mA | VVM = 13.5 V; nSLEEP=1 | 7 |
| Internal logic regulator voltage | VDVDD | 3 | 3.3 | 3.5 | V | 2-mA load | 7 |
| Internal logic regulator voltage | VDVDD | 2.9 | 3.2 | 3.5 | V | 30-mA load, VVM = 13.5 V | 7 |
| Internal logic regulator voltage | VAVDD | 4.7 | 5 | 5.3 | V | 2-mA load | 7 |
| Internal logic regulator voltage | VAVDD | 4.6 | 5 | 5.3 | V | 30-mA load, VVM = 13.5 V | 7 |
| VCP operating voltage | VVCP | 22.5 | 23.5 | 24.5 | V | VVM = 13.5 V; IVCP = 0 to 12 mA | 7 |
| VCP operating voltage | VVCP | 13.7 | 14 | 14.8 | V | VVM = 8 V; IVCP = 0 to 10 mA | 7 |
| VCP operating voltage | VVCP | 8.9 | 9.1 | 9.5 | V | VVM = 5.5 V; IVCP = 0 to 8 mA | 7 |
| Input logic-low voltage | VIL | 0 | | 0.8 | V | | 8 |
| Input logic-high voltage | VIH | 1.5 | | 5.25 | V | | 8 |
| Input logic-low current | IIL | -5 | | 5 | µA | VIN = 0 V | 8 |
| Pulldown resistance | RPD | 64 | 100 | 173 | kΩ | IN1/PH, IN2/EN, nSLEEP, nSCS, SCLK, SDI | 8 |
| Output logic-low voltage | VOL | | | 0.1 | V | IO = 2 mA | 8 |
| High-side VGS gate drive (gate-to-source) | VGSH | 10.5 | | 11.5 | V | VVM > 13.5 V; VGSH with respect to SHx | 8 |
| High-side VGS gate drive (gate-to-source) | VGSH | 5.7 | | 6.8 | V | VVM = 8 V; VGSH with respect to SHx | 8 |
| High-side VGS gate drive (gate-to-source) | VGSH | 3.4 | | 4 | V | VVM = 5.5 V; VGSH with respect to SHx | 8 |
| Gate-drive clamping voltage positive | VC(GS) | 16.3 | 17 | 17.8 | V | Positive clamping voltage | 12 |
| Gate-drive clamping voltage negative | VC(GS) | -1 | -0.7 | -0.5 | V | Negative clamping voltage | 12 |
| Amplifier gain (DRV8703-Q1) | AV | 9.75 | 10 | 10.25 | V/V | GAIN_CS = 00; 10 < VSP < 450 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 19.3 | 19.8 | 20.3 | V/V | GAIN_CS = 01; 60 < VSP < 225 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 38.4 | 39.4 | 40.4 | V/V | GAIN_CS = 10; 10 < VSP < 112 mV; VSN = GND | 11 |
| Amplifier gain (DRV8703-Q1) | AV | 73 | 78 | 81 | V/V | GAIN_CS = 11; 10 < VSP < 56 mV; VSN = GND | 11 |
| VM undervoltage lockout (falling) | V(UVLO2) | 5.25 | | 5.45 | V | VM falling; UVLO2 report | 11 |
| VM undervoltage lockout (rising) | V(UVLO2) | 5.4 | | 5.65 | V | VM rising; UVLO2 recovery | 11 |
| Overcurrent protection trip level, measured by sense amplifier | VSP(OCP) | 0.8 | 1 | 1.2 | V | VSP with respect to GND | 11 |
| Thermal warning temperature | T(OTW) | 120 | 135 | 145 | °C | Die temperature TJ | 11 |
| Charge-pump switching frequency | fS(VCP) | 200 | 400 | 700 | kHz | VM > UVLO2 | 12 |
| Overcurrent deglitch time | t(OCP) | 3.7 | 4 | 4.3 | µs | | 13 |
| Overcurrent retry time | t(RETRY) | 2.8 | 3 | 3.2 | ms | | 13 |
| Minimum SPI clock period | t(CLK) | 100 | | | ns | | 12 |
| SDI input data setup time | t(SU_SDI) | 20 | | | ns | | 12 |
| SDI input data hold time | t(HD_SDI) | 30 | | | ns | | 12 |
| Junction-to-ambient thermal resistance | RθJA | | 32.9 | | °C/W | | 7 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 19.6 | | °C/W | | 7 |
| Junction-to-board thermal resistance | RθJB | | 6.8 | | °C/W | | 7 |
| Junction-to-top characterization parameter | ψJT | | 0.3 | | °C/W | | 7 |
| Junction-to-board characterization parameter | ψJB | | 6.8 | | °C/W | | 7 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 1.8 | | °C/W | | 7 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | SL2 23 23 I Low-side source. Connect this pin to the low-side FET source. SN 22 22 I Shunt-amplifier negative input. Connect this pin to the current-sense resistor. | 5 |
## CAD (KiCad official)
- Symbol: `DRV8703QRHBTQ1`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files: `drv8703qrhbtq1-etched.step` / `drv8703qrhbtq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8703qrhbtq1.step` / `drv8703qrhbtq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8703-q1.pdf) (63 pp, sha256 `41f247d459b34028`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8703qrhbtq1-datasheet.pdf)