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DRV8702QRHBRQ1
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Texas Instruments Motor Driver ICs, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+70@@ -0,0 +1,70 @@+# DRV8702QRHBRQ1++**Texas Instruments** · Motor Driver ICs · HVQFN-32-EP(5x5)++DRV8702QRHBRQ1 from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GND | power_in | Device ground connection point. |+| 2 | IN1/PH | input | Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor. |+| 3 | IN2/EN | input | Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor. |+| 4 | GND | power_in | Device ground connection point. |+| 5 | IDRIVE | input | Gate driver current setting pin; applied resistance or voltage sets gate drive peak source and sink currents. |+| 6 | VDS | input | VDS over-current monitor threshold setting pin; applied resistance adjusts VDS(OCP) threshold voltage for per-FET protection. |+| 7 | GND | power_in | Device ground connection point. |+| 8 | nSLEEP | input | Device sleep mode control; logic low enables low-power sleep mode with all FETs in high-impedance state; internally connected to pull-down resistor. |+| 9 | GND | power_in | Device ground connection point. |+| 10 | nFAULT | tri_state | Fault indicator output; pulled to logic low when fault condition detected; open-drain output requiring external pull-up resistor. |+| 11 | MODE | input | Mode control pin; pull low for H-bridge mode, high for independent half-bridge mode, or leave floating for PWM mode; mode is latched on power-up or sleep exit; internally connected to pull-up and pull-down resistors. |+| 12 | DVDD | power_out | 3.3V regulated logic supply output for internal digital circuits; bypass to ground with 6.3V 1µF ceramic capacitor. |+| 13 | GND | power_in | Device ground connection point. |+| 14 | AVDD | power_out | 5V regulated analog supply output for current amplifier and sensing circuits; bypass to ground with 6.3V 1µF ceramic capacitor. |+| 15 | VREF | power_in | Current reference input voltage; sets PWM chopper current regulation level for motor current limiting. |+| 16 | SO | output | Current amplifier output; voltage proportional to sensed current with gain AV ≈20V/V; do not place capacitance exceeding 1nF on this pin. |+| 17 | GND | power_in | Device ground connection point. |+| 18 | GH1 | output | High-side gate driver output for bridge 1; connect to gate of high-side NMOS FET Q(HS1). |+| 19 | SH1 | input | High-side source node connection for bridge 1; connect to source of high-side FET Q(HS1); used for VDS monitoring. |+| 20 | GL1 | output | Low-side gate driver output for bridge 1; connect to gate of low-side NMOS FET Q(LS1). |+| 21 | SP | input | Current sense amplifier positive input; connect to high side of external current sense resistor. |+| 22 | SN | input | Current sense amplifier negative input; connect to low side of external current sense resistor for over-current detection. |+| 23 | SL2 | input | Low-side source node connection for bridge 2; connect to source of low-side FET Q(LS2); used for VDS monitoring. |+| 24 | GL2 | output | Low-side gate driver output for bridge 2; connect to gate of low-side NMOS FET Q(LS2). |+| 25 | SH2 | input | High-side source node connection for bridge 2; connect to source of high-side FET Q(HS2); used for VDS monitoring. |+| 26 | GH2 | output | High-side gate driver output for bridge 2; connect to gate of high-side NMOS FET Q(HS2). |+| 27 | VDRAIN | input | High-side FET drain connection node; common connection point where high-side FET drains connect; shared between H-bridge channels. |+| 28 | VM | power_in | Motor power supply input (5.5V to 45V); requires 0.1µF ceramic bypass and minimum 10µF bulk capacitors to ground for EMI filtering. |+| 29 | VCP | power_out | Charge pump output for high-side gate drive voltage; connect 16V rated 1µF ceramic capacitor between VCP and VM pins. |+| 30 | CPH | output | Charge pump high switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins. |+| 31 | CPL | output | Charge pump low switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins. |+| 32 | NC | unconnected | No connection; no internal connection; leave unconnected or tied to ground optionally. |+| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HVQFN-32-EP(5x5) |+| Category | Power Supply Chip |+| Pins | 33 |++## CAD (KiCad official)++- Symbol: `DRV8702QRHBRQ1`+- Footprint: `Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm`+- 3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)+- 3D model files: `drv8702qrhbrq1-etched.step` / `drv8702qrhbrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8702qrhbrq1.step` / `drv8702qrhbrq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8702-q1) (63 pp, sha256 `ab99f0978331e55f`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8702qrhbrq1-datasheet.pdf)
page.jsonadded+309@@ -0,0 +1,309 @@+{+ "slug": "drv8702qrhbrq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Motor Driver ICs, HVQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "drv8702qrhbrq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8702qrhbrq1.kicad_sym",+ "drv8702qrhbrq1.kicad_mod",+ "drv8702qrhbrq1.glb",+ "drv8702qrhbrq1.step",+ "drv8702qrhbrq1.lbr",+ "docs/hero.png",+ "docs/drv8702qrhbrq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "drv8702qrhbrq1-hero.glb",+ "drv8702qrhbrq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "DRV8702QRHBRQ1",+ "manufacturer": "Texas Instruments",+ "package": "HVQFN-32-EP(5x5)",+ "pin_count": 33,+ "category": "Power Supply Chip",+ "subcategory": "Motor Driver ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8702-q1",+ "parts": {+ "symbol": "drv8702qrhbrq1.kicad_sym",+ "footprint": "drv8702qrhbrq1.kicad_mod",+ "model_3d": "drv8702qrhbrq1-hero.glb",+ "model_3d_plain": "drv8702qrhbrq1.glb",+ "model_3d_step": "drv8702qrhbrq1-etched.step",+ "model_3d_step_plain": "drv8702qrhbrq1.step",+ "lbr": "drv8702qrhbrq1.lbr"+ },+ "distributor_links": {+ "lcsc": 181608,+ "digikey": "296-45153-2-ND",+ "mouser": "595-DRV8702QRHBRQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T09:04:27Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-45153-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DRV8702QRHBRQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "2",+ "name": "IN1/PH",+ "type": "input",+ "description": "Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor."+ },+ {+ "number": "3",+ "name": "IN2/EN",+ "type": "input",+ "description": "Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor."+ },+ {+ "number": "4",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "5",+ "name": "IDRIVE",+ "type": "input",+ "description": "Gate driver current setting pin; applied resistance or voltage sets gate drive peak source and sink currents."+ },+ {+ "number": "6",+ "name": "VDS",+ "type": "input",+ "description": "VDS over-current monitor threshold setting pin; applied resistance adjusts VDS(OCP) threshold voltage for per-FET protection."+ },+ {+ "number": "7",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "8",+ "name": "nSLEEP",+ "type": "input",+ "description": "Device sleep mode control; logic low enables low-power sleep mode with all FETs in high-impedance state; internally connected to pull-down resistor."+ },+ {+ "number": "9",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "10",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator output; pulled to logic low when fault condition detected; open-drain output requiring external pull-up resistor."+ },+ {+ "number": "11",+ "name": "MODE",+ "type": "input",+ "description": "Mode control pin; pull low for H-bridge mode, high for independent half-bridge mode, or leave floating for PWM mode; mode is latched on power-up or sleep exit; internally connected to pull-up and pull-down resistors."+ },+ {+ "number": "12",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3V regulated logic supply output for internal digital circuits; bypass to ground with 6.3V 1µF ceramic capacitor."+ },+ {+ "number": "13",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "14",+ "name": "AVDD",+ "type": "power_out",+ "description": "5V regulated analog supply output for current amplifier and sensing circuits; bypass to ground with 6.3V 1µF ceramic capacitor."+ },+ {+ "number": "15",+ "name": "VREF",+ "type": "power_in",+ "description": "Current reference input voltage; sets PWM chopper current regulation level for motor current limiting."+ },+ {+ "number": "16",+ "name": "SO",+ "type": "output",+ "description": "Current amplifier output; voltage proportional to sensed current with gain AV ≈20V/V; do not place capacitance exceeding 1nF on this pin."+ },+ {+ "number": "17",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground connection point."+ },+ {+ "number": "18",+ "name": "GH1",+ "type": "output",+ "description": "High-side gate driver output for bridge 1; connect to gate of high-side NMOS FET Q(HS1)."+ },+ {+ "number": "19",+ "name": "SH1",+ "type": "input",+ "description": "High-side source node connection for bridge 1; connect to source of high-side FET Q(HS1); used for VDS monitoring."+ },+ {+ "number": "20",+ "name": "GL1",+ "type": "output",+ "description": "Low-side gate driver output for bridge 1; connect to gate of low-side NMOS FET Q(LS1)."+ },+ {+ "number": "21",+ "name": "SP",+ "type": "input",+ "description": "Current sense amplifier positive input; connect to high side of external current sense resistor."+ },+ {+ "number": "22",+ "name": "SN",+ "type": "input",+ "description": "Current sense amplifier negative input; connect to low side of external current sense resistor for over-current detection."+ },+ {+ "number": "23",+ "name": "SL2",+ "type": "input",+ "description": "Low-side source node connection for bridge 2; connect to source of low-side FET Q(LS2); used for VDS monitoring."+ },+ {+ "number": "24",+ "name": "GL2",+ "type": "output",+ "description": "Low-side gate driver output for bridge 2; connect to gate of low-side NMOS FET Q(LS2)."+ },+ {+ "number": "25",+ "name": "SH2",+ "type": "input",+ "description": "High-side source node connection for bridge 2; connect to source of high-side FET Q(HS2); used for VDS monitoring."+ },+ {+ "number": "26",+ "name": "GH2",+ "type": "output",+ "description": "High-side gate driver output for bridge 2; connect to gate of high-side NMOS FET Q(HS2)."+ },+ {+ "number": "27",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side FET drain connection node; common connection point where high-side FET drains connect; shared between H-bridge channels."+ },+ {+ "number": "28",+ "name": "VM",+ "type": "power_in",+ "description": "Motor power supply input (5.5V to 45V); requires 0.1µF ceramic bypass and minimum 10µF bulk capacitors to ground for EMI filtering."+ },+ {+ "number": "29",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output for high-side gate drive voltage; connect 16V rated 1µF ceramic capacitor between VCP and VM pins."+ },+ {+ "number": "30",+ "name": "CPH",+ "type": "output",+ "description": "Charge pump high switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins."+ },+ {+ "number": "31",+ "name": "CPL",+ "type": "output",+ "description": "Charge pump low switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins."+ },+ {+ "number": "32",+ "name": "NC",+ "type": "unconnected",+ "description": "No connection; no internal connection; leave unconnected or tied to ground optionally."+ },+ {+ "number": "33",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 33 added from the footprint"+ ],+ "pages_sent": 50,+ "cost_usd": 0.4009,+ "at": "2026-10-03T09:03:57"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8702-q1",+ "pages": 63,+ "sha256": "ab99f0978331e55f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 33,+ "described": 33,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}