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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DRV8702QRHBRQ1

Texas Instruments · Motor Driver ICs · HVQFN-32-EP(5x5)

DRV8702QRHBRQ1 from Texas Instruments, in a HVQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND	power_in	Device ground connection point.
2	IN1/PH	input	Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor.
3	IN2/EN	input	Input control pin whose logic function depends on MODE pin setting; internally connected to pull-down resistor.
4	GND	power_in	Device ground connection point.
5	IDRIVE	input	Gate driver current setting pin; applied resistance or voltage sets gate drive peak source and sink currents.
6	VDS	input	VDS over-current monitor threshold setting pin; applied resistance adjusts VDS(OCP) threshold voltage for per-FET protection.
7	GND	power_in	Device ground connection point.
8	nSLEEP	input	Device sleep mode control; logic low enables low-power sleep mode with all FETs in high-impedance state; internally connected to pull-down resistor.
9	GND	power_in	Device ground connection point.
10	nFAULT	tri_state	Fault indicator output; pulled to logic low when fault condition detected; open-drain output requiring external pull-up resistor.
11	MODE	input	Mode control pin; pull low for H-bridge mode, high for independent half-bridge mode, or leave floating for PWM mode; mode is latched on power-up or sleep exit; internally connected to pull-up and pull-down resistors.
12	DVDD	power_out	3.3V regulated logic supply output for internal digital circuits; bypass to ground with 6.3V 1µF ceramic capacitor.
13	GND	power_in	Device ground connection point.
14	AVDD	power_out	5V regulated analog supply output for current amplifier and sensing circuits; bypass to ground with 6.3V 1µF ceramic capacitor.
15	VREF	power_in	Current reference input voltage; sets PWM chopper current regulation level for motor current limiting.
16	SO	output	Current amplifier output; voltage proportional to sensed current with gain AV ≈20V/V; do not place capacitance exceeding 1nF on this pin.
17	GND	power_in	Device ground connection point.
18	GH1	output	High-side gate driver output for bridge 1; connect to gate of high-side NMOS FET Q(HS1).
19	SH1	input	High-side source node connection for bridge 1; connect to source of high-side FET Q(HS1); used for VDS monitoring.
20	GL1	output	Low-side gate driver output for bridge 1; connect to gate of low-side NMOS FET Q(LS1).
21	SP	input	Current sense amplifier positive input; connect to high side of external current sense resistor.
22	SN	input	Current sense amplifier negative input; connect to low side of external current sense resistor for over-current detection.
23	SL2	input	Low-side source node connection for bridge 2; connect to source of low-side FET Q(LS2); used for VDS monitoring.
24	GL2	output	Low-side gate driver output for bridge 2; connect to gate of low-side NMOS FET Q(LS2).
25	SH2	input	High-side source node connection for bridge 2; connect to source of high-side FET Q(HS2); used for VDS monitoring.
26	GH2	output	High-side gate driver output for bridge 2; connect to gate of high-side NMOS FET Q(HS2).
27	VDRAIN	input	High-side FET drain connection node; common connection point where high-side FET drains connect; shared between H-bridge channels.
28	VM	power_in	Motor power supply input (5.5V to 45V); requires 0.1µF ceramic bypass and minimum 10µF bulk capacitors to ground for EMI filtering.
29	VCP	power_out	Charge pump output for high-side gate drive voltage; connect 16V rated 1µF ceramic capacitor between VCP and VM pins.
30	CPH	output	Charge pump high switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins.
31	CPL	output	Charge pump low switching node; connect 0.1µF X7R ceramic capacitor (rated for VM voltage) between CPH and CPL pins.
32	NC	unconnected	No connection; no internal connection; leave unconnected or tied to ground optionally.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HVQFN-32-EP(5x5)
Category	Power Supply Chip
Pins	33

CAD (KiCad official)

Symbol: DRV8702QRHBRQ1
Footprint: Package_DFN_QFN:HVQFN-32-1EP_5x5mm_P0.5mm_EP3.1x3.1mm
3D model: HVQFN-32-EP(5x5) (KiCad packages3D, STEP)
3D model files: drv8702qrhbrq1-etched.step / drv8702qrhbrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8702qrhbrq1.step / drv8702qrhbrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (63 pp, sha256 ab99f0978331e55f, retrieved 2026-10-03, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF