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DRV8436PRGER

Texas Instruments · Stepper Motor Driver · VQFN-24-EP(4x4)

DRV8436PRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VM	power_in	Motor supply input, recommended range 4.5 V to 48 V; bypass with two 0.01 µF ceramic capacitors rated VM, placed close to the pin, plus a bulk capacitor rated above the operating voltage.
2	PGND	power_in	Power ground; the two PGND pins are internally shorted and must be connected to the system ground on the PCB.
3	AOUT1	output	Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
4	AOUT2	output	Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
5	BOUT2	output	Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
6	BOUT1	output	Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
7	PGND	power_in	Power ground; internally shorted to the other PGND pin and connected to the system ground on the PCB.
8	VM	power_in	Motor supply input, recommended range 4.5 V to 48 V; bypass to GND with a 0.01 µF ceramic capacitor rated VM close to the pin and share the bulk capacitor.
9	GND	power_in	Device ground; connect to the system ground.
10	DVDD	power_out	Internal 5 V logic regulator output, supplying up to 2 mA; bypass to GND with a 0.47 µF X7R ceramic capacitor rated 6.3 V or 10 V.
11	nFAULT	output	Open-drain fault indicator that is pulled low during a fault and requires an external pull-up resistor; sink current is limited to 10 mA maximum.
12	VREFB	input	Reference voltage input that sets the full-scale chopping current of bridge B (IFS = VREFB / 2.2 V/A); maximum 3.3 V.
13	VREFA	input	Reference voltage input that sets the full-scale chopping current of bridge A (IFS = VREFA / 2.2 V/A); maximum 3.3 V.
14	TOFF	input	Four-level input that sets the PWM off-time: GND = 7 µs, DVDD = 16 µs, high-impedance = 24 µs, 330 kΩ to GND = 32 µs.
15	BDECAY	input	Four-level input that sets the decay mode of bridge B (smart-tune dynamic, slow, 30% mixed, or fast decay).
16	ADECAY	input	Four-level input that sets the decay mode of bridge A (smart-tune dynamic, slow, 30% mixed, or fast decay).
17	BIN2	input	Bridge B PWM input that controls the H-bridge B state; internal pull-down, logic low maximum 0.6 V and logic high 1.5 V to 5.5 V.
18	BIN1	input	Bridge B PWM input that controls the H-bridge B state; internal pull-down, logic low maximum 0.6 V and logic high 1.5 V to 5.5 V.
19	AIN2	input	Bridge A PWM input that controls the H-bridge A state; internal pull-down, logic low maximum 0.6 V and logic high 1.5 V to 5.5 V.
20	AIN1	input	Bridge A PWM input that controls the H-bridge A state; internal pull-down, logic low maximum 0.6 V and logic high 1.5 V to 5.5 V.
21	nSLEEP	input	Sleep-mode input: logic high enables the device and logic low places it in low-power sleep; internal pull-down, and it must not be tied to DVDD.
22	CPL	passive	Charge-pump negative switch node; a 0.022 µF X7R ceramic capacitor rated VM is connected between CPH and CPL.
23	CPH	passive	Charge-pump switch node; a 0.022 µF X7R ceramic capacitor rated VM is connected between CPH and CPL.
24	VCP	power_out	Charge-pump output, nominally VM + 5 V; connect a 0.22 µF 16 V X7R ceramic capacitor between VCP and VM.
25	PAD	power_in	Exposed thermal pad that must be soldered to the PCB and connected to the system ground.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Motor Driver ICs
Pins	25

CAD (KiCad official)

Symbol: DRV8436PRGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: drv8436prger-etched.step / drv8436prger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8436prger.step / drv8436prger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (46 pp, sha256 32cfac267bdda8d5, retrieved 2026-10-08, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF