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DRV8434SRGER

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Texas Instruments Stepper Motor Driver, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8434SRGER

Texas Instruments · Stepper Motor Driver · VQFN-24(4x4)

DRV8434SRGER from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Motor supply pin, operating range 4.5 V to 48 V, bypassed to PGND with a 0.01 µF ceramic capacitor rated for VM placed close to the pin and a bulk capacitor rated for VM.
2 PGND power_in Power ground pin, connect to system ground.
3 AOUT1 output Winding A output, connect to a stepper motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
4 AOUT2 output Winding A output, connect to a stepper motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
5 BOUT2 output Winding B output, connect to a stepper motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
6 BOUT1 output Winding B output, connect to a stepper motor winding; continuous phase-node voltage is limited to -1 V to VM + 1 V.
7 PGND power_in Power ground pin, connect to system ground.
8 VM power_in Motor supply pin, operating range 4.5 V to 48 V, bypassed to PGND with a 0.01 µF ceramic capacitor rated for VM placed close to the pin and a bulk capacitor rated for VM.
9 GND power_in Device ground pin, connect to system ground.
10 DVDD power_out Logic supply from the internal linear regulator (nominal 5 V, up to 2 mA load), bypassed to GND with a 0.47 µF to 1 µF X7R 6.3 V or 10 V ceramic capacitor.
11 nFAULT output Open-drain fault indicator, pulled low on a fault and requiring an external pull-up to 5 V, 3.3 V or 1.8 V; open-drain output current is limited to 10 mA.
12 VREF power_in Current-setting reference input, maximum 3.3 V; can be driven from DVDD through a resistor divider.
13 nSCS input Active-low serial chip select with internal pull-up to DVDD.
14 VSDO power_in Supply pin for the SDO output, connected to an external voltage chosen to match the required logic level.
15 SDO output Push-pull serial data output, shifting data out on the rising edge of SCLK.
16 SDI input Serial data input, captured on the falling edge of SCLK.
17 SCLK input Serial clock input; data is shifted out and captured on the rising and falling edges of this pin.
18 STEP input Step input, each rising edge advances the indexer by one step; internal pull-down resistor.
19 DIR input Direction input whose logic level sets the step direction; internal pull-down resistor.
20 ENABLE input Logic low disables the outputs (high-impedance), logic high enables them; internal pull-up to DVDD.
21 nSLEEP input Sleep mode input: logic high enables the device, logic low enters low-power sleep; internal pull-down, and a low pulse clears latched faults.
22 CPL passive Charge pump negative switching node; connect a low-ESR X7R 0.022 µF ceramic capacitor rated for VM between CPH and CPL.
23 CPH passive Charge pump switch node; connect a low-ESR X7R 0.022 µF ceramic capacitor rated for VM between CPH and CPL.
24 VCP power_out Charge pump output, connect to VM through a X7R 0.22 µF 16 V ceramic capacitor.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Motor Driver ICs
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VM for normal DC operation VVM 4.5 48 V 5
Logic-level input voltage VI 0 5.5 V 5
VREF voltage VVREF 0.05 3.3 V 5
Applied STEP signal frequency fSTEP 0 500 kHz 5
Motor full-scale current (xOUTx) IFS 0 2.5 A 5
Motor RMS current (xOUTx) Irms 0 1.8 A 5
Operating ambient temperature TA -40 125 °C 5
Operating junction temperature TJ -40 150 °C 5
VM operating supply current IVM 5 6.5 mA ENABLE = 1，nSLEEP = 1，无电机负载 6
VM sleep-mode supply current IVMQ 2 4 µA nSLEEP = 0 6
Internal regulator voltage VDVDD (6V < VVM < 48V) VDVDD 4.75 5 5.25 V 无外部负载，6V < VVM < 48V 6
Internal regulator voltage VDVDD (VVM = 4.5V) VDVDD 4.2 4.35 V 无外部负载，VVM = 4.5V 6
Input logic-low voltage VIL 0 0.6 V 6
Input logic-high voltage VIH 1.5 5.5 V 6
Input logic-low current (nSCS) IIL1 8 12 µA VIN = 0V 6
Input logic-low current (other pins) IIL -1 1 µA VIN = 0V 6
SDO internal pull-down resistance RPD,SDO 30 60 Ω 5 mA 负载，以 GND 为基准 6
SDO internal pull-up resistance RPU,SDO 30 60 Ω 5mA 负载，以 VSDO 为基准 6
SDO leakage current ISDO -1 1 µA SDO = VSDO 和 0V 6
nFAULT output high-level leakage current IOH -1 1 µA 6
High-side FET on-resistance (25°C) RDS(ON) 165 200 mΩ TJ = 25°C、IO = -1A 6
High-side FET on-resistance (125°C) RDS(ON) 250 300 mΩ TJ = 125°C、IO = -1A 6
High-side FET on-resistance (150°C) RDS(ON) 280 350 mΩ TJ = 150°C、IO = -1A 6
Low-side FET on-resistance (25°C) RDS(ON) 165 200 mΩ TJ = 25°C、IO = 1A 6
Low-side FET on-resistance (125°C) RDS(ON) 250 300 mΩ TJ = 125°C、IO = 1A 6
Low-side FET on-resistance (150°C) RDS(ON) 280 350 mΩ TJ = 150°C、IO = 1A 6
Wake-up time tWAKE 0.8 1.2 ms nSLEEP = 1 至输出转换 6
Turn-on time tON 0.8 1.2 ms VM > UVLO 至输出转换 6
nSLEEP reset pulse (clears faults) tRESET 20 40 µs nSLEEP 低电平至清除故障 6
Transconductance gain KV 1.254 1.32 1.386 V/A VREF = 3.3V 6
Current trip accuracy (0.25A < IO < 0.5A) ΔITRIP -12 12 % 0.25A < IO < 0.5A 7
Current trip accuracy (0.5A < IO < 1A) ΔITRIP -6 6 % 0.5A < IO < 1A 7
Current trip accuracy (1A < IO < 2.5A) ΔITRIP -4 4 % 1A < IO < 2.5A 7
AOUT and BOUT current matching IO,CH -2.5 2.5 % IO = 2.5A 7
VM UVLO lock threshold (falling) VUVLO 4.1 4.25 4.35 V VM 下降，UVLO 下降 7
VM UVLO lock threshold (rising) VUVLO 4.2 4.35 4.45 V VM 上升，UVLO 上升 7
Overtemperature warning threshold TOTW 135 150 165 °C 内核温度 TJ 7
Thermal shutdown threshold TOTSD 150 165 180 °C 内核温度 TJ 7
Charge pump enable time (ENABLE 0/1 to output transition) tEN 5 µs ENABLE = 0/1 至输出转换 6
Charge pump switching frequency f(VCP) 360 kHz VVM > UVLO；nSLEEP = 1 6
Input logic hysteresis VHYS 150 mV 6
nFAULT output low-level voltage VOL 0.5 V IO = 5mA 6
VREF leakage current IVREF 8.25 µA VREF = 3.3V 7
VM UVLO reset threshold VRST 3.9 V VM 下降，器件复位，SPI 通信 7
Overcurrent protection threshold IOCP 4 A 流经任何 FET 的电流 7
Overcurrent deglitch time tOCP 2 µs 7
Overcurrent retry time tRETRY 4 ms OCP_MODE = 1b 7
Open-load detection time tOL 50 ms EN_OL = 1b 7
Open-load current threshold IOL 75 mA EN_OL = 1b 7
UVLO hysteresis (rising to falling threshold) VUVLO,HYS 100 mV 上升至下降阈值 7
Output slew rate tSR 240 V/µs VVM = 24V、IO = 1A，在 10% 至 90% 之间 6
Sleep-mode entry time tSLEEP 120 µs nSLEEP = 0 至睡眠模式 6
Thermal shutdown hysteresis THYS_OTSD 20 °C 内核温度 TJ 7
Overtemperature warning hysteresis THYS_OTW 20 °C 内核温度 TJ 7
Junction-to-ambient thermal resistance (RGE 24-pin) RθJA 39 °C/W 5
Junction-to-case (top) thermal resistance (RGE 24-pin) RθJC(top) 28.9 °C/W 5
Junction-to-board thermal resistance (RGE 24-pin) RθJB 16 °C/W 5
Junction-to-top characterization parameter (RGE 24-pin) ψJT 0.4 °C/W 5
Junction-to-board characterization parameter (RGE 24-pin) ψJB 15.9 °C/W 5
Junction-to-case (bottom) thermal resistance (RGE 24-pin) RθJC(bot) 3.4 °C/W 5

CAD (KiCad official)

  • Symbol: DRV8434SRGER
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8434srger-etched.step / drv8434srger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8434srger.step / drv8434srger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (72 pp, sha256 25f2e8540e04853a, retrieved 2026-10-21, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF