component
DRV8434SPWPR
Public Made by Adomby adom
Texas Instruments Stepper Motor Driver, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8434SPWPR
Texas Instruments · Stepper Motor Driver · HTSSOP-28
DRV8434SPWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output, connected to VM through a X7R 0.22µF 16V ceramic capacitor placed as close to the pin as possible. |
| 2 | VM | power_in | Motor supply pin (4.5 V to 48 V operating range), bypassed to PGND with a 0.01µF ceramic capacitor rated for VM and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground, connected to system ground. |
| 4 | AOUT1 | output | Winding A output, connected to the stepper motor winding. |
| 5 | AOUT1 | output | Winding A output, connected to the stepper motor winding. |
| 6 | AOUT2 | output | Winding A output, connected to the stepper motor winding. |
| 7 | AOUT2 | output | Winding A output, connected to the stepper motor winding. |
| 8 | BOUT2 | output | Winding B output, connected to the stepper motor winding. |
| 9 | BOUT2 | output | Winding B output, connected to the stepper motor winding. |
| 10 | BOUT1 | output | Winding B output, connected to the stepper motor winding. |
| 11 | BOUT1 | output | Winding B output, connected to the stepper motor winding. |
| 12 | PGND | power_in | Power ground, connected to system ground. |
| 13 | VM | power_in | Motor supply pin (4.5 V to 48 V operating range), bypassed to PGND with a 0.01µF ceramic capacitor rated for VM and a bulk capacitor rated for VM. |
| 14 | GND | power_in | Device ground, connected to system ground. |
| 15 | DVDD | power_out | Logic supply from the internal regulator (nominal 5 V), bypassed to GND with a 0.47µF to 1µF X7R 6.3 V or 10 V ceramic capacitor; the LDO supplies at most 2 mA. |
| 16 | nFAULT | output | Open-drain fault indication output, pulled low during a fault and requiring an external pull-up resistor to 5 V, 3.3 V or 1.8 V. |
| 17 | VREF | power_in | Current setpoint reference input with a maximum of 3.3 V; DVDD can be divided through a resistor divider to supply VREF. |
| 18 | nSCS | input | Active-low serial chip select with an internal pull-up to DVDD. |
| 19 | VSDO | power_in | Supply pin for the SDO output, connected to an external voltage chosen for the required logic level. |
| 20 | SDO | output | Push-pull serial data output, shifted out on the rising edge of SCLK. |
| 21 | SDI | input | Serial data input, captured on the falling edge of SCLK. |
| 22 | SCLK | input | Serial clock input; data is shifted out and captured on the corresponding rising and falling edges of this pin. |
| 23 | STEP | input | Step input, where each rising edge advances the indexer by one step; internal pull-down resistor. |
| 24 | DIR | input | Direction input whose logic level sets the stepping direction; internal pull-down resistor. |
| 25 | ENABLE | input | Logic low disables the device outputs and logic high enables them; internal pull-up to DVDD. |
| 26 | nSLEEP | input | Logic high enables the device and logic low places it in low-power sleep mode; a low pulse on this pin clears faults; internal pull-down resistor. |
| 27 | CPL | passive | Charge pump flying-capacitor node, connected to CPH through a X7R 0.022µF ceramic capacitor rated for VM. |
| 28 | CPH | passive | Charge pump switch node, connected to CPL through a X7R 0.022µF ceramic capacitor rated for VM. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Motor Driver ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VVM 可确保正常（直流）运行的电源电压范围 | VVM | 4.5 | 48 | V | 5 | ||
| VI 逻辑电平输入电压 | VI | 0 | 5.5 | V | 5 | ||
| VVREF VREF 电压 | VVREF | 0.05 | 3.3 | V | 5 | ||
| fSTEP 施加的 STEP 信号 | fSTEP | 0 | 500 | kHz | STEP 输入工作频率最高可达 500kHz，但系统带宽受电机负载限制 | 5 | |
| IFS 电机满量程电流 (xOUTx) | IFS | 0 | 2.5 | A | 必须遵守功耗和热限值 | 5 | |
| Irms 电机均方根电流 (xOUTx) | Irms | 0 | 1.8 | A | 必须遵守功耗和热限值 | 5 | |
| TA 工作环境温度 | TA | -40 | 125 | °C | 5 | ||
| TJ 工作结温 | TJ | -40 | 150 | °C | 5 | ||
| VM 工作电源电流 | IVM | 5 | 6.5 | mA | ENABLE = 1，nSLEEP = 1，无电机负载 | 6 | |
| VM 睡眠模式电源电流 | IVMQ | 2 | 4 | μA | nSLEEP = 0 | 6 | |
| nSLEEP 复位脉冲 | tRESET | 20 | 40 | μs | nSLEEP 低电平至清除故障 | 6 | |
| 唤醒时间 | tWAKE | 0.8 | 1.2 | ms | nSLEEP = 1 至输出转换 | 6 | |
| 开通时间 | tON | 0.8 | 1.2 | ms | VM > UVLO 至输出转换 | 6 | |
| 内部稳压器电压 (VDVDD) | VDVDD | 4.75 | 5 | 5.25 | V | 无外部负载，6V < VVM < 48V | 6 |
| 内部稳压器电压 (VDVDD) | VDVDD | 4.2 | 4.35 | V | 无外部负载，VVM = 4.5V | 6 | |
| 输入逻辑低电平电压 | VIL | 0 | 0.6 | V | 6 | ||
| 输入逻辑高电平电压 | VIH | 1.5 | 5.5 | V | 6 | ||
| 输入逻辑低电平电流 (nSCS) | IIL1 | 8 | 12 | μA | VIN = 0V | 6 | |
| 输入逻辑低电平电流（其他引脚） | IIL | -1 | 1 | μA | VIN = 0V | 6 | |
| 输入逻辑高电平电流 (nSCS) | IIH1 | 500 | nA | VIN = DVDD | 6 | ||
| 输入逻辑高电平电流（其他引脚） | IIH | 100 | μA | VIN = 5V | 6 | ||
| SDO 内部下拉电阻 | RPD,SDO | 30 | 60 | Ω | 5mA 负载，以 GND 为基准 | 6 | |
| SDO 内部上拉电阻 | RPU,SDO | 30 | 60 | Ω | 5mA 负载，以 VSDO 为基准 | 6 | |
| SDO 泄漏电流 | ISDO | -1 | 1 | μA | SDO = VSDO 和 0V | 6 | |
| 输出逻辑低电平电压 (nFAULT) | VOL | 0.5 | V | IO = 5mA | 6 | ||
| 输出逻辑高电平泄漏电流 (nFAULT) | IOH | -1 | 1 | μA | 6 | ||
| 高侧 FET 导通电阻 (TJ = 25°C) | RDS(ON) | 165 | 200 | mΩ | TJ = 25°C、IO = -1A | 6 | |
| 高侧 FET 导通电阻 (TJ = 125°C) | RDS(ON) | 250 | 300 | mΩ | TJ = 125°C、IO = -1A | 6 | |
| 高侧 FET 导通电阻 (TJ = 150°C) | RDS(ON) | 280 | 350 | mΩ | TJ = 150°C、IO = -1A | 6 | |
| 低侧 FET 导通电阻 (TJ = 25°C) | RDS(ON) | 165 | 200 | mΩ | TJ = 25°C、IO = 1A | 6 | |
| 低侧 FET 导通电阻 (TJ = 125°C) | RDS(ON) | 250 | 300 | mΩ | TJ = 125°C、IO = 1A | 6 | |
| 低侧 FET 导通电阻 (TJ = 150°C) | RDS(ON) | 280 | 350 | mΩ | TJ = 150°C、IO = 1A | 6 | |
| 跨阻增益 | KV | 1.254 | 1.32 | 1.386 | V/A | VREF = 3.3V | 6 |
| VREF 泄漏电流 | IVREF | 8.25 | µA | VREF = 3.3V | 7 | ||
| 电流跳变精度 | ΔITRIP | -12 | 12 | % | 0.25A < IO < 0.5A | 7 | |
| 电流跳变精度 | ΔITRIP | -6 | 6 | % | 0.5A < IO < 1A | 7 | |
| 电流跳变精度 | ΔITRIP | -4 | 4 | % | 1A < IO < 2.5A | 7 | |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | 2.5 | % | IO = 2.5A | 7 | |
| VM UVLO 锁定 (VM 下降) | VUVLO | 4.1 | 4.25 | 4.35 | V | VM 下降，UVLO 下降 | 7 |
| VM UVLO 锁定 (VM 上升) | VUVLO | 4.2 | 4.35 | 4.45 | V | VM 上升，UVLO 上升 | 7 |
| 过热警告 (内核温度 TJ) | TOTW | 135 | 150 | 165 | °C | 内核温度 TJ | 7 |
| 热关断 (内核温度 TJ) | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 7 |
| SPI 就绪 | t(READY) | 1 | ms | VM > VRST | 7 | ||
| SCLK 最小周期 | t(CLK) | 100 | ns | 7 | |||
| SCLK 最短高电平时间 | t(CLKH) | 50 | ns | 7 | |||
| SCLK 最短低电平时间 | t(CLKL) | 50 | ns | 7 | |||
| SDI 输入设置时间 | tsu(SDI) | 20 | ns | 7 | |||
| SDI 输入保持时间 | th(SDI) | 30 | ns | 7 | |||
| SDO 输出延迟时间 | td(SDO) | 30 | ns | SCLK 高电平至 SDO 有效，CL = 20pF | 7 | ||
| nSCS 输入设置时间 | tsu(nSCS) | 50 | ns | 7 | |||
| nSCS 输入保持时间 | th(nSCS) | 50 | ns | 7 | |||
| 低电平有效前的 nSCS 最短高电平时间 | t(HI_nSCS) | 2 | µs | 7 | |||
| nSCS 禁用时间 | tdis(nSCS) | 10 | ns | nSCS 高电平至 SDO 高阻抗 | 7 | ||
| 结至环境热阻 (PWP 28 引脚) | RθJA | 29.7 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 结至外壳（顶部）热阻 (PWP 28 引脚) | RθJC(top) | 23 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 结至电路板热阻 (PWP 28 引脚) | RθJB | 9.3 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 结至顶部特征参数 (PWP 28 引脚) | ψJT | 0.3 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 结至电路板特征参数 (PWP 28 引脚) | ψJB | 9.2 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 结至外壳（底部）热阻 (PWP 28 引脚) | RθJC(bot) | 2.4 | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 | ||
| 过流保护 (流经任何 FET 的电流) | IOCP | 4 | A | 流经任何 FET 的电流 | 7 |
CAD (KiCad official)
- Symbol:
DRV8434SPWPR - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files:
drv8434spwpr-etched.step/drv8434spwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8434spwpr.step/drv8434spwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (72 pp, sha256
25f2e8540e04853a, retrieved 2026-10-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8434SPWPR
**Texas Instruments** · Stepper Motor Driver · HTSSOP-28
DRV8434SPWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output, connected to VM through a X7R 0.22µF 16V ceramic capacitor placed as close to the pin as possible. |
| 2 | VM | power_in | Motor supply pin (4.5 V to 48 V operating range), bypassed to PGND with a 0.01µF ceramic capacitor rated for VM and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground, connected to system ground. |
| 4 | AOUT1 | output | Winding A output, connected to the stepper motor winding. |
| 5 | AOUT1 | output | Winding A output, connected to the stepper motor winding. |
| 6 | AOUT2 | output | Winding A output, connected to the stepper motor winding. |
| 7 | AOUT2 | output | Winding A output, connected to the stepper motor winding. |
| 8 | BOUT2 | output | Winding B output, connected to the stepper motor winding. |
| 9 | BOUT2 | output | Winding B output, connected to the stepper motor winding. |
| 10 | BOUT1 | output | Winding B output, connected to the stepper motor winding. |
| 11 | BOUT1 | output | Winding B output, connected to the stepper motor winding. |
| 12 | PGND | power_in | Power ground, connected to system ground. |
| 13 | VM | power_in | Motor supply pin (4.5 V to 48 V operating range), bypassed to PGND with a 0.01µF ceramic capacitor rated for VM and a bulk capacitor rated for VM. |
| 14 | GND | power_in | Device ground, connected to system ground. |
| 15 | DVDD | power_out | Logic supply from the internal regulator (nominal 5 V), bypassed to GND with a 0.47µF to 1µF X7R 6.3 V or 10 V ceramic capacitor; the LDO supplies at most 2 mA. |
| 16 | nFAULT | output | Open-drain fault indication output, pulled low during a fault and requiring an external pull-up resistor to 5 V, 3.3 V or 1.8 V. |
| 17 | VREF | power_in | Current setpoint reference input with a maximum of 3.3 V; DVDD can be divided through a resistor divider to supply VREF. |
| 18 | nSCS | input | Active-low serial chip select with an internal pull-up to DVDD. |
| 19 | VSDO | power_in | Supply pin for the SDO output, connected to an external voltage chosen for the required logic level. |
| 20 | SDO | output | Push-pull serial data output, shifted out on the rising edge of SCLK. |
| 21 | SDI | input | Serial data input, captured on the falling edge of SCLK. |
| 22 | SCLK | input | Serial clock input; data is shifted out and captured on the corresponding rising and falling edges of this pin. |
| 23 | STEP | input | Step input, where each rising edge advances the indexer by one step; internal pull-down resistor. |
| 24 | DIR | input | Direction input whose logic level sets the stepping direction; internal pull-down resistor. |
| 25 | ENABLE | input | Logic low disables the device outputs and logic high enables them; internal pull-up to DVDD. |
| 26 | nSLEEP | input | Logic high enables the device and logic low places it in low-power sleep mode; a low pulse on this pin clears faults; internal pull-down resistor. |
| 27 | CPL | passive | Charge pump flying-capacitor node, connected to CPH through a X7R 0.022µF ceramic capacitor rated for VM. |
| 28 | CPH | passive | Charge pump switch node, connected to CPL through a X7R 0.022µF ceramic capacitor rated for VM. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Motor Driver ICs |
| Pins | 29 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VVM 可确保正常（直流）运行的电源电压范围 | VVM | 4.5 | | 48 | V | | 5 |
| VI 逻辑电平输入电压 | VI | 0 | | 5.5 | V | | 5 |
| VVREF VREF 电压 | VVREF | 0.05 | | 3.3 | V | | 5 |
| fSTEP 施加的 STEP 信号 | fSTEP | 0 | | 500 | kHz | STEP 输入工作频率最高可达 500kHz，但系统带宽受电机负载限制 | 5 |
| IFS 电机满量程电流 (xOUTx) | IFS | 0 | | 2.5 | A | 必须遵守功耗和热限值 | 5 |
| Irms 电机均方根电流 (xOUTx) | Irms | 0 | | 1.8 | A | 必须遵守功耗和热限值 | 5 |
| TA 工作环境温度 | TA | -40 | | 125 | °C | | 5 |
| TJ 工作结温 | TJ | -40 | | 150 | °C | | 5 |
| VM 工作电源电流 | IVM | | 5 | 6.5 | mA | ENABLE = 1，nSLEEP = 1，无电机负载 | 6 |
| VM 睡眠模式电源电流 | IVMQ | | 2 | 4 | μA | nSLEEP = 0 | 6 |
| nSLEEP 复位脉冲 | tRESET | | 20 | 40 | μs | nSLEEP 低电平至清除故障 | 6 |
| 唤醒时间 | tWAKE | | 0.8 | 1.2 | ms | nSLEEP = 1 至输出转换 | 6 |
| 开通时间 | tON | | 0.8 | 1.2 | ms | VM > UVLO 至输出转换 | 6 |
| 内部稳压器电压 (VDVDD) | VDVDD | 4.75 | 5 | 5.25 | V | 无外部负载，6V < VVM < 48V | 6 |
| 内部稳压器电压 (VDVDD) | VDVDD | 4.2 | | 4.35 | V | 无外部负载，VVM = 4.5V | 6 |
| 输入逻辑低电平电压 | VIL | 0 | | 0.6 | V | | 6 |
| 输入逻辑高电平电压 | VIH | 1.5 | | 5.5 | V | | 6 |
| 输入逻辑低电平电流 (nSCS) | IIL1 | | 8 | 12 | μA | VIN = 0V | 6 |
| 输入逻辑低电平电流（其他引脚） | IIL | -1 | | 1 | μA | VIN = 0V | 6 |
| 输入逻辑高电平电流 (nSCS) | IIH1 | | | 500 | nA | VIN = DVDD | 6 |
| 输入逻辑高电平电流（其他引脚） | IIH | | | 100 | μA | VIN = 5V | 6 |
| SDO 内部下拉电阻 | RPD,SDO | | 30 | 60 | Ω | 5mA 负载，以 GND 为基准 | 6 |
| SDO 内部上拉电阻 | RPU,SDO | | 30 | 60 | Ω | 5mA 负载，以 VSDO 为基准 | 6 |
| SDO 泄漏电流 | ISDO | -1 | | 1 | μA | SDO = VSDO 和 0V | 6 |
| 输出逻辑低电平电压 (nFAULT) | VOL | | | 0.5 | V | IO = 5mA | 6 |
| 输出逻辑高电平泄漏电流 (nFAULT) | IOH | -1 | | 1 | μA | | 6 |
| 高侧 FET 导通电阻 (TJ = 25°C) | RDS(ON) | | 165 | 200 | mΩ | TJ = 25°C、IO = -1A | 6 |
| 高侧 FET 导通电阻 (TJ = 125°C) | RDS(ON) | | 250 | 300 | mΩ | TJ = 125°C、IO = -1A | 6 |
| 高侧 FET 导通电阻 (TJ = 150°C) | RDS(ON) | | 280 | 350 | mΩ | TJ = 150°C、IO = -1A | 6 |
| 低侧 FET 导通电阻 (TJ = 25°C) | RDS(ON) | | 165 | 200 | mΩ | TJ = 25°C、IO = 1A | 6 |
| 低侧 FET 导通电阻 (TJ = 125°C) | RDS(ON) | | 250 | 300 | mΩ | TJ = 125°C、IO = 1A | 6 |
| 低侧 FET 导通电阻 (TJ = 150°C) | RDS(ON) | | 280 | 350 | mΩ | TJ = 150°C、IO = 1A | 6 |
| 跨阻增益 | KV | 1.254 | 1.32 | 1.386 | V/A | VREF = 3.3V | 6 |
| VREF 泄漏电流 | IVREF | | | 8.25 | µA | VREF = 3.3V | 7 |
| 电流跳变精度 | ΔITRIP | -12 | | 12 | % | 0.25A < IO < 0.5A | 7 |
| 电流跳变精度 | ΔITRIP | -6 | | 6 | % | 0.5A < IO < 1A | 7 |
| 电流跳变精度 | ΔITRIP | -4 | | 4 | % | 1A < IO < 2.5A | 7 |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | | 2.5 | % | IO = 2.5A | 7 |
| VM UVLO 锁定 (VM 下降) | VUVLO | 4.1 | 4.25 | 4.35 | V | VM 下降，UVLO 下降 | 7 |
| VM UVLO 锁定 (VM 上升) | VUVLO | 4.2 | 4.35 | 4.45 | V | VM 上升，UVLO 上升 | 7 |
| 过热警告 (内核温度 TJ) | TOTW | 135 | 150 | 165 | °C | 内核温度 TJ | 7 |
| 热关断 (内核温度 TJ) | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 7 |
| SPI 就绪 | t(READY) | | | 1 | ms | VM > VRST | 7 |
| SCLK 最小周期 | t(CLK) | 100 | | | ns | | 7 |
| SCLK 最短高电平时间 | t(CLKH) | 50 | | | ns | | 7 |
| SCLK 最短低电平时间 | t(CLKL) | 50 | | | ns | | 7 |
| SDI 输入设置时间 | tsu(SDI) | 20 | | | ns | | 7 |
| SDI 输入保持时间 | th(SDI) | 30 | | | ns | | 7 |
| SDO 输出延迟时间 | td(SDO) | | | 30 | ns | SCLK 高电平至 SDO 有效，CL = 20pF | 7 |
| nSCS 输入设置时间 | tsu(nSCS) | 50 | | | ns | | 7 |
| nSCS 输入保持时间 | th(nSCS) | 50 | | | ns | | 7 |
| 低电平有效前的 nSCS 最短高电平时间 | t(HI_nSCS) | 2 | | | µs | | 7 |
| nSCS 禁用时间 | tdis(nSCS) | | | 10 | ns | nSCS 高电平至 SDO 高阻抗 | 7 |
| 结至环境热阻 (PWP 28 引脚) | RθJA | | 29.7 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 结至外壳（顶部）热阻 (PWP 28 引脚) | RθJC(top) | | 23 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 结至电路板热阻 (PWP 28 引脚) | RθJB | | 9.3 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 结至顶部特征参数 (PWP 28 引脚) | ψJT | | 0.3 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 结至电路板特征参数 (PWP 28 引脚) | ψJB | | 9.2 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 结至外壳（底部）热阻 (PWP 28 引脚) | RθJC(bot) | | 2.4 | | °C/W | PWP (HTSSOP) 28 引脚 列 | 5 |
| 过流保护 (流经任何 FET 的电流) | IOCP | | 4 | | A | 流经任何 FET 的电流 | 7 |
## CAD (KiCad official)
- Symbol: `DRV8434SPWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `drv8434spwpr-etched.step` / `drv8434spwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8434spwpr.step` / `drv8434spwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8434s) (72 pp, sha256 `25f2e8540e04853a`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8434spwpr-datasheet.pdf)