component
DRV8434PWPR
Public Made by Adomby adom
Texas Instruments Stepper Motor Driver, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8434PWPR
Texas Instruments · Stepper Motor Driver · HTSSOP-28
DRV8434PWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output; connect an X7R 0.22µF 16V ceramic capacitor between VCP and VM. |
| 2 | VM | power_in | Motor supply voltage, 4.5 V to 48 V for normal DC operation (absolute maximum 50 V); bypass to PGND with two 0.01µF ceramic capacitors (one per pin) and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground; connect to system ground. |
| 4 | AOUT1 | output | Winding A output; connect to a stepper motor winding. |
| 5 | AOUT1 | output | Winding A output; connect to a stepper motor winding. |
| 6 | AOUT2 | output | Winding A output; connect to a stepper motor winding. |
| 7 | AOUT2 | output | Winding A output; connect to a stepper motor winding. |
| 8 | BOUT2 | output | Winding B output; connect to a stepper motor winding. |
| 9 | BOUT2 | output | Winding B output; connect to a stepper motor winding. |
| 10 | BOUT1 | output | Winding B output; connect to a stepper motor winding. |
| 11 | BOUT1 | output | Winding B output; connect to a stepper motor winding. |
| 12 | PGND | power_in | Power ground; connect to system ground. |
| 13 | VM | power_in | Motor supply voltage, 4.5 V to 48 V for normal DC operation (absolute maximum 50 V); bypass to PGND with the same capacitors as pin 2. |
| 14 | GND | power_in | Device ground; connect to system ground. |
| 15 | DVDD | power_out | Internal 5 V logic regulator output (2 mA maximum external load); bypass to GND with a 0.47µF to 1µF X7R 6.3 V or 10 V ceramic capacitor. |
| 16 | nFAULT | output | Open-drain fault indicator that goes low on a fault and requires an external pull-up to 5 V, 3.3 V or 1.8 V (absolute maximum sink current 10 mA). |
| 17 | VREF | power_in | Current-set reference input with a maximum of 3.3 V; DVDD can be divided down through a resistor divider to supply it. |
| 18 | M0 | input | Microstep mode select (tri-level input) with an internal pull-down resistor. |
| 19 | TOFF | input | Quad-level input that sets the PWM off-time and, in smart tune ripple control mode, the ripple current. |
| 20 | DECAY1 | input | Decay mode select (tri-level input); when Hi-Z, smart tune dynamic decay is selected regardless of DECAY0. |
| 21 | DECAY0 | input | Decay mode select (tri-level input) together with DECAY1. |
| 22 | M1 | input | Microstep mode select (quad-level input). |
| 23 | STEP | input | Step input; each rising edge advances the indexer by one step, with an internal pull-down resistor. |
| 24 | DIR | input | Direction input whose logic level sets the step direction, with an internal pull-down resistor. |
| 25 | ENABLE | input | Logic low disables the outputs, logic high enables them; internally pulled up to DVDD, and it also selects the OCP and OTSD response (latched when Hi-Z, automatic retry when high). |
| 26 | nSLEEP | input | Logic high enables the device and logic low puts it in low-power sleep; internal pull-down, a low pulse clears faults, and it must not be tied to DVDD. |
| 27 | CPL | passive | Charge pump negative switch node; connect a VM-rated X7R 0.022µF ceramic capacitor between CPH and CPL. |
| 28 | CPH | passive | Charge pump switch node; connect a VM-rated X7R 0.022µF ceramic capacitor between CPH and CPL. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Motor Driver ICs |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
DRV8434PWPR - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files:
drv8434pwpr-etched.step/drv8434pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8434pwpr.step/drv8434pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
d73d3e37312bc8d5, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8434PWPR
**Texas Instruments** · Stepper Motor Driver · HTSSOP-28
DRV8434PWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output; connect an X7R 0.22µF 16V ceramic capacitor between VCP and VM. |
| 2 | VM | power_in | Motor supply voltage, 4.5 V to 48 V for normal DC operation (absolute maximum 50 V); bypass to PGND with two 0.01µF ceramic capacitors (one per pin) and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground; connect to system ground. |
| 4 | AOUT1 | output | Winding A output; connect to a stepper motor winding. |
| 5 | AOUT1 | output | Winding A output; connect to a stepper motor winding. |
| 6 | AOUT2 | output | Winding A output; connect to a stepper motor winding. |
| 7 | AOUT2 | output | Winding A output; connect to a stepper motor winding. |
| 8 | BOUT2 | output | Winding B output; connect to a stepper motor winding. |
| 9 | BOUT2 | output | Winding B output; connect to a stepper motor winding. |
| 10 | BOUT1 | output | Winding B output; connect to a stepper motor winding. |
| 11 | BOUT1 | output | Winding B output; connect to a stepper motor winding. |
| 12 | PGND | power_in | Power ground; connect to system ground. |
| 13 | VM | power_in | Motor supply voltage, 4.5 V to 48 V for normal DC operation (absolute maximum 50 V); bypass to PGND with the same capacitors as pin 2. |
| 14 | GND | power_in | Device ground; connect to system ground. |
| 15 | DVDD | power_out | Internal 5 V logic regulator output (2 mA maximum external load); bypass to GND with a 0.47µF to 1µF X7R 6.3 V or 10 V ceramic capacitor. |
| 16 | nFAULT | output | Open-drain fault indicator that goes low on a fault and requires an external pull-up to 5 V, 3.3 V or 1.8 V (absolute maximum sink current 10 mA). |
| 17 | VREF | power_in | Current-set reference input with a maximum of 3.3 V; DVDD can be divided down through a resistor divider to supply it. |
| 18 | M0 | input | Microstep mode select (tri-level input) with an internal pull-down resistor. |
| 19 | TOFF | input | Quad-level input that sets the PWM off-time and, in smart tune ripple control mode, the ripple current. |
| 20 | DECAY1 | input | Decay mode select (tri-level input); when Hi-Z, smart tune dynamic decay is selected regardless of DECAY0. |
| 21 | DECAY0 | input | Decay mode select (tri-level input) together with DECAY1. |
| 22 | M1 | input | Microstep mode select (quad-level input). |
| 23 | STEP | input | Step input; each rising edge advances the indexer by one step, with an internal pull-down resistor. |
| 24 | DIR | input | Direction input whose logic level sets the step direction, with an internal pull-down resistor. |
| 25 | ENABLE | input | Logic low disables the outputs, logic high enables them; internally pulled up to DVDD, and it also selects the OCP and OTSD response (latched when Hi-Z, automatic retry when high). |
| 26 | nSLEEP | input | Logic high enables the device and logic low puts it in low-power sleep; internal pull-down, a low pulse clears faults, and it must not be tied to DVDD. |
| 27 | CPL | passive | Charge pump negative switch node; connect a VM-rated X7R 0.022µF ceramic capacitor between CPH and CPL. |
| 28 | CPH | passive | Charge pump switch node; connect a VM-rated X7R 0.022µF ceramic capacitor between CPH and CPL. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Motor Driver ICs |
| Pins | 29 |
## CAD (KiCad official)
- Symbol: `DRV8434PWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `drv8434pwpr-etched.step` / `drv8434pwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8434pwpr.step` / `drv8434pwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8434) (54 pp, sha256 `d73d3e37312bc8d5`, retrieved 2026-10-08, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8434pwpr-datasheet.pdf)