component
DRV8434EPWPR
Public Made by Adomby adom
Texas Instruments Stepper Motor Driver, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
DRV8434EPWPR
Texas Instruments · Stepper Motor Driver · HTSSOP-28-EP
DRV8434EPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output; connect a X7R, 0.22-μF, 16-V ceramic capacitor to VM. |
| 2 | VM | power_in | Power supply for the motor supply voltage; bypass to PGND with two 0.01-μF ceramic capacitors (one per pin) plus a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground; connect to system ground. |
| 4 | AOUT1 | output | Winding A output; connect to motor winding. |
| 5 | AOUT1 | output | Winding A output; connect to motor winding. |
| 6 | AOUT2 | output | Winding A output; connect to motor winding. |
| 7 | AOUT2 | output | Winding A output; connect to motor winding. |
| 8 | BOUT2 | output | Winding B output; connect to motor winding. |
| 9 | BOUT2 | output | Winding B output; connect to motor winding. |
| 10 | BOUT1 | output | Winding B output; connect to motor winding. |
| 11 | BOUT1 | output | Winding B output; connect to motor winding. |
| 12 | PGND | power_in | Power ground; connect to system ground. |
| 13 | VM | power_in | Power supply for the motor supply voltage; bypass to PGND with two 0.01-μF ceramic capacitors (one per pin) plus a bulk capacitor rated for VM. |
| 14 | GND | power_in | Device ground; connect to system ground. |
| 15 | DVDD | power_in | Logic supply voltage; connect a X7R, 0.47-μF to 1-μF, 6.3-V or 10-V rated ceramic capacitor to GND. |
| 16 | nFAULT | output | Fault indication open-drain output, pulled logic low during a fault condition and requiring an external pullup resistor. |
| 17 | VREFB | input | Reference voltage input; the voltage on this pin sets the full-scale chopping current in H-bridge B. |
| 18 | VREFA | input | Reference voltage input; the voltage on this pin sets the full-scale chopping current in H-bridge A. |
| 19 | TOFF | input | Quad-level pin that sets the decay mode off-time during current chopping. |
| 20 | BDECAY | input | Quad-level decay mode setting pin for bridge B. |
| 21 | ADECAY | input | Quad-level decay mode setting pin for bridge A. |
| 22 | BPH | input | Bridge B phase input; logic high drives current from BOUT1 to BOUT2. |
| 23 | BEN | input | Bridge B enable input; logic high enables bridge B and logic low disables the bridge to Hi-Z. |
| 24 | APH | input | Bridge A phase input; logic high drives current from AOUT1 to AOUT2. |
| 25 | AEN | input | Bridge A enable input; logic high enables bridge A and logic low disables the bridge to Hi-Z. |
| 26 | nSLEEP | input | Sleep mode input; logic high enables the device and logic low enters low-power sleep mode, with an internal pulldown resistor and an nSLEEP low pulse clearing faults. |
| 27 | CPL | passive | Charge pump switching node; connect a X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL. |
| 28 | CPH | passive | Charge pump switching node; connect a X7R, 0.022-μF, VM-rated ceramic capacitor from CPH to CPL. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Motor Driver ICs |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VM | -0.3 | 50 | V | 7 | ||
| Internal regulator voltage | DVDD | -0.3 | 5.75 | V | 7 | ||
| Control pin voltage | -0.3 | 5.75 | V | APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2, nFAULT, ADECAY, BDECAY, TOFF | 7 | ||
| Open drain output current | 0 | 10 | mA | nFAULT | 7 | ||
| Reference input pin voltage | VREFA, VREFB | -0.3 | 5.75 | V | 7 | ||
| Operating ambient temperature | TA | -40 | 125 | °C | 7 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Supply voltage range for normal (DC) operation | VVM | 4.5 | 48 | V | 8 | ||
| Logic level input voltage | VI | 0 | 5.5 | V | 8 | ||
| Reference rms voltage range | VREF | 0.05 | 3.3 | V | VREFA, VREFB | 8 | |
| Applied PWM signal | ƒPWM | 0 | 100 | kHz | APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2 | 8 | |
| Motor full-scale current | IFS | 0 | 2.5 | A | xOUTx | 8 | |
| Motor RMS current | Irms | 0 | 1.8 | A | xOUTx | 8 | |
| Operating ambient temperature | TA | -40 | 125 | °C | 8 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 8 | ||
| VM operating supply current | IVM | 5 | 6.5 | mA | nSLEEP = 1, No motor load | 9 | |
| VM sleep mode supply current | IVMQ | 2 | 4 | μA | nSLEEP = 0 | 9 | |
| nSLEEP reset pulse | tRESET | 20 | 40 | μs | nSLEEP low to clear fault | 9 | |
| Wake-up time | tWAKE | 0.8 | 1.2 | ms | nSLEEP = 1 to output transition | 9 | |
| Turn-on time | tON | 0.8 | 1.2 | ms | VM > UVLO to output transition | 9 | |
| Internal regulator voltage | VDVDD | 4.75 | 5 | 5.25 | V | No external load, 6 V < VVM < 48 V | 9 |
| Internal regulator voltage | VDVDD | 4.2 | 4.35 | V | No external load, VVM = 4.5 V | 9 | |
| Input logic-low voltage | VIL | 0 | 0.6 | V | 9 | ||
| Input logic-high voltage | VIH | 1.5 | 5.5 | V | 9 | ||
| Input logic-low current | IIL | -1 | 1 | μA | VIN = 0 V | 9 | |
| Input logic-high current | IIH | 100 | μA | VIN = 5 V | 9 | ||
| Propagation delay | tPD | 800 | ns | 9 | |||
| Quad-level input voltage | VI2 | 1 | 1.25 | 1.4 | V | 330kΩ ± 5% to GND | 9 |
| Input Hi-Z voltage | VI3 | 1.8 | 2 | 2.2 | V | Hi-Z (>500kΩ to GND) | 9 |
| Input logic-high voltage | VI4 | 2.7 | 5.5 | V | Tied to DVDD | 9 | |
| Output logic-low voltage | VOL | 0.5 | V | IO = 5 mA | 9 | ||
| High-side FET on resistance | RDS(ONH) | 165 | 200 | mΩ | TJ = 25 °C, IO = -1 A | 9 | |
| High-side FET on resistance | RDS(ONH) | 250 | 300 | mΩ | TJ = 125 °C, IO = -1 A | 9 | |
| High-side FET on resistance | RDS(ONH) | 280 | 350 | mΩ | TJ = 150 °C, IO = -1 A | 9 | |
| Low-side FET on resistance | RDS(ONL) | 165 | 200 | mΩ | TJ = 25 °C, IO = 1 A | 9 | |
| Low-side FET on resistance | RDS(ONL) | 250 | 300 | mΩ | TJ = 125 °C, IO = 1 A | 9 | |
| Low-side FET on resistance | RDS(ONL) | 280 | 350 | mΩ | TJ = 150 °C, IO = 1 A | 9 | |
| Transimpedance gain | KV | 1.254 | 1.32 | 1.386 | V/A | VREF = 3.3 V | 9 |
| Current trip accuracy | ΔITRIP | -12 | 12 | % | 0.25 A < IO < 0.5 A | 10 | |
| Current trip accuracy | ΔITRIP | -6 | 6 | % | 0.5 A < IO < 1 A | 10 | |
| Current trip accuracy | ΔITRIP | -4 | 4 | % | 1 A < IO < 2.5 A | 10 | |
| AOUT and BOUT current matching | IO,CH | -2.5 | 2.5 | % | IO = 2.5 A | 10 | |
| VM UVLO lockout | VUVLO | 4.1 | 4.25 | 4.35 | V | VM falling, UVLO falling | 10 |
| VM UVLO lockout | VUVLO | 4.2 | 4.35 | 4.45 | V | VM rising, UVLO rising | 10 |
| Thermal shutdown | TOTSD | 150 | 165 | 180 | °C | Die temperature TJ | 10 |
| Sleep time | tSLEEP | 120 | μs | nSLEEP = 0 to sleep-mode | 9 | ||
| Charge pump switching frequency | f(VCP) | 360 | kHz | VVM > UVLO; nSLEEP = 1 | 9 | ||
| Input logic hysteresis | VHYS | 150 | mV | 9 | |||
| Output pull-up current | IO | 10 | μA | 9 | |||
| Output slew rate | tSR | 240 | V/µs | VM = 24V, IO = 1 A, Between 10% and 90% | 9 | ||
| PWM off-time | tOFF | 7 | μs | TOFF = 0 | 10 | ||
| PWM off-time | tOFF | 16 | μs | TOFF = 1 | 10 | ||
| PWM off-time | tOFF | 24 | μs | TOFF = Hi-Z | 10 | ||
| PWM off-time | tOFF | 32 | μs | TOFF = 330 kΩ to GND | 10 | ||
| Overcurrent protection | IOCP | 4 | A | Current through any FET | 10 | ||
| Thermal resistance junction-to-ambient | RθJA | 29.7 | °C/W | PWP (HTSSOP), 28 pins | 8 | ||
| Thermal resistance junction-to-case (top) | RθJC(top) | 23 | °C/W | PWP (HTSSOP), 28 pins | 8 | ||
| Thermal resistance junction-to-board | RθJB | 9.3 | °C/W | PWP (HTSSOP), 28 pins | 8 | ||
| Thermal resistance junction-to-case (bottom) | RθJC(bot) | 2.4 | °C/W | PWP (HTSSOP), 28 pins | 8 |
CAD (KiCad official)
- Symbol:
DRV8434EPWPR - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
drv8434epwpr-etched.step/drv8434epwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8434epwpr.step/drv8434epwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
72f2741db1b1fa9f, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).