# DRV8434APWPR

**Texas Instruments** · Stepper Motor Driver · HTSSOP-28

DRV8434APWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge-pump output, connected to VM through an X7R 0.22µF 16V ceramic capacitor. |
| 2 | VM | power_in | Motor supply voltage, operating range 4.5 V to 48 V, bypassed to PGND with two 0.01µF ceramic capacitors (one per pin) and a bulk capacitor rated above VM; absolute maximum 50 V. |
| 3 | PGND | power_in | Power ground, connected to system ground. |
| 4 | AOUT1 | output | Winding A output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 5 | AOUT1 | output | Winding A output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 6 | AOUT2 | output | Winding A output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 7 | AOUT2 | output | Winding A output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 8 | BOUT2 | output | Winding B output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 9 | BOUT2 | output | Winding B output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 10 | BOUT1 | output | Winding B output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 11 | BOUT1 | output | Winding B output connected to the stepper motor winding; continuous node voltage limited to -1 V to VM + 1 V. |
| 12 | PGND | power_in | Power ground, connected to system ground. |
| 13 | VM | power_in | Motor supply voltage, operating range 4.5 V to 48 V, bypassed to PGND with two 0.01µF ceramic capacitors (one per pin) and a bulk capacitor rated above VM; absolute maximum 50 V. |
| 14 | GND | power_in | Device ground, connected to system ground. |
| 15 | DVDD | power_out | Internal logic regulator output, nominally 5 V with up to 2 mA load, bypassed to GND with a 0.47µF to 1µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 16 | nFAULT | output | Open-drain fault output, pulled low when a fault is detected and requires an external pull-up; sink current limited to 10 mA. |
| 17 | VREF | power_in | Current-set reference input, maximum 3.3 V; can be driven from DVDD through a resistor divider. |
| 18 | M0 | input | Three-level microstep mode setting input that selects the step mode per Table 7-2. |
| 19 | STL_REP | output | Open-drain stall report output that requires a pull-up resistor, goes high on stall and low on successful learning; can also be pulled low externally to disable stall reporting; sink current limited to 10 mA. |
| 20 | TRQ_CNT/STL_TH | bidirectional | Torque-count analog output or stall-threshold analog input depending on STL_MODE; requires a 1 nF capacitor to GND. |
| 21 | STL_MODE | input | Four-level input that programs the stall detection mode; a 330 kΩ resistor to GND disables stall detection. |
| 22 | M1 | input | Four-level microstep mode setting input that selects the step mode per Table 7-2. |
| 23 | STEP | input | Step input; each rising edge advances the translator one step, with an operating frequency up to 500 kHz and an internal pull-down. |
| 24 | DIR | input | Direction input whose logic level sets the step direction, with an internal pull-down. |
| 25 | ENABLE | input | Logic low disables the outputs and logic high enables them; a high-impedance level enables 8x torque-count scaling. |
| 26 | nSLEEP | input | Sleep mode control, logic high enables the device and logic low enters low-power sleep; a low pulse clears latched faults; internal pull-down; must not be connected to DVDD. |
| 27 | CPL | passive | Charge-pump negative switch node, connected to CPH through an X7R 0.022µF ceramic capacitor rated for VM. |
| 28 | CPH | passive | Charge-pump switch node, connected to CPL through an X7R 0.022µF ceramic capacitor rated for VM. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Motor Driver ICs |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Motor supply voltage (VM, DC operation) | VVM | 4.5 |  | 48 | V |  | 6 |
| Logic level input voltage | VI | 0 |  | 5.5 | V |  | 6 |
| VREF voltage | VVREF | 0.05 |  | 3.3 | V |  | 6 |
| Applied STEP signal frequency | fSTEP | 0 |  | 500 | kHz |  | 6 |
| Motor full-scale current (xOUTx) | IFS | 0 |  | 2.5 | A |  | 6 |
| Motor RMS current (xOUTx) | Irms | 0 |  | 1.8 | A |  | 6 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 6 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 6 |
| VM operating supply current | IVM |  | 5 | 6.5 | mA | ENABLE = 1, nSLEEP = 1, no motor load | 7 |
| VM sleep mode supply current | IVMQ |  | 2 | 4 | μA | nSLEEP = 0 | 7 |
| nSLEEP reset pulse (clear faults) | tRESET | 20 |  | 40 | μs | nSLEEP low to clear fault | 7 |
| Wake-up time | tWAKE | 0.8 |  | 1.2 | ms | nSLEEP = 1 to output transition | 7 |
| Turn-on time | tON | 0.8 |  | 1.2 | ms | VM > UVLO to output transition | 7 |
| Internal regulator voltage (DVDD) | VDVDD | 4.75 | 5 | 5.25 | V | No external load, 6V < VVM < 48V | 7 |
| Internal regulator voltage (DVDD) at low VM | VDVDD | 4.2 |  | 4.35 | V | No external load, VVM = 4.5V | 7 |
| Logic input low voltage (STEP, DIR, nSLEEP) | VIL | 0 |  | 0.6 | V |  | 7 |
| Logic input high voltage (STEP, DIR, nSLEEP) | VIH | 1.5 |  | 5.5 | V |  | 7 |
| Logic input low current (STEP, DIR, nSLEEP) | IIL | -1 |  | 1 | μA | VIN = 0V | 7 |
| Three-level input low voltage (M0, ENABLE) | VI1 | 0 |  | 0.6 | V | Connected to GND | 7 |
| Three-level input high-Z voltage (M0, ENABLE) | VI2 | 1.8 | 2 | 2.2 | V | High-impedance state | 7 |
| Three-level input high voltage (M0, ENABLE) | VI3 | 2.7 |  | 5.5 | V | Connected to DVDD | 7 |
| Four-level input low voltage (M1, STL_MODE) | VI1 | 0 |  | 0.6 | V | Connected to GND | 7 |
| Four-level input 330kΩ state voltage (M1, STL_MODE) | VI2 | 1 | 1.25 | 1.4 | V | 330kΩ ±5% to GND | 7 |
| Four-level input high-Z voltage (M1, STL_MODE) | VI3 | 1.8 | 2 | 2.2 | V | High-impedance state | 7 |
| Four-level input high voltage (M1, STL_MODE) | VI4 | 2.7 |  | 5.5 | V | Connected to DVDD | 7 |
| Control output logic high leakage current (nFAULT, STL_REP) | IOH | -1 |  | 1 | μA |  | 8 |
| STL_REP input low voltage | VIL | 0 |  | 0.6 | V | STL_REP pulled low to disable stall reporting | 8 |
| STL_REP input high voltage | VIH | 1.5 |  | 5.5 | V | STL_REP pulled high to enable stall reporting | 8 |
| High-side FET on-resistance | RDS(ON) |  | 165 | 200 | mΩ | TJ = 25°C, IO = -1A | 8 |
| High-side FET on-resistance | RDS(ON) |  | 250 | 300 | mΩ | TJ = 125°C, IO = -1A | 8 |
| High-side FET on-resistance | RDS(ON) |  | 280 | 350 | mΩ | TJ = 150°C, IO = -1A | 8 |
| Low-side FET on-resistance | RDS(ON) |  | 165 | 200 | mΩ | TJ = 25°C, IO = 1A | 8 |
| Low-side FET on-resistance | RDS(ON) |  | 250 | 300 | mΩ | TJ = 125°C, IO = 1A | 8 |
| Low-side FET on-resistance | RDS(ON) |  | 280 | 350 | mΩ | TJ = 150°C, IO = 1A | 8 |
| Transconductance gain (current sense) | KV | 1.254 | 1.32 | 1.386 | V/A | VREF = 3.3V | 8 |
| Current trip accuracy | ΔITRIP | -12 |  | 12 | % | 0.25A < IO < 0.5A | 8 |
| Current trip accuracy | ΔITRIP | -6 |  | 6 | % | 0.5A < IO < 1A | 8 |
| Current trip accuracy | ΔITRIP | -4 |  | 4 | % | 1A < IO < 2.5A | 8 |
| AOUT and BOUT current matching | IO,CH | -2.5 |  | 2.5 | % | IO = 2.5A | 8 |
| VM UVLO threshold (falling) | VUVLO | 4.1 | 4.25 | 4.35 | V | VM falling | 8 |
| VM UVLO threshold (rising) | VUVLO | 4.2 | 4.35 | 4.45 | V | VM rising | 8 |
| Thermal shutdown temperature | TOTSD | 150 | 165 | 180 | °C | Core temperature TJ | 8 |
| Junction-to-ambient thermal resistance | RθJA |  | 29.7 |  | °C/W | PWP (HTSSOP-28) | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 23 |  | °C/W | PWP (HTSSOP-28) | 6 |
| Junction-to-board thermal resistance | RθJB |  | 9.3 |  | °C/W | PWP (HTSSOP-28) | 6 |
| Junction-to-top characterization parameter | ψJT |  | 0.3 |  | °C/W | PWP (HTSSOP-28) | 6 |
| Junction-to-board characterization parameter | ψJB |  | 9.2 |  | °C/W | PWP (HTSSOP-28) | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 2.4 |  | °C/W | PWP (HTSSOP-28) | 6 |

## CAD (KiCad official)

- Symbol: `DRV8434APWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `drv8434apwpr-etched.step` / `drv8434apwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8434apwpr.step` / `drv8434apwpr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8434a) (52 pp, sha256 `662fdbf7dfc53054`, retrieved 2026-10-18, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8434apwpr-datasheet.pdf)