component

DRV8428PPWPR

Public Made by Adom

by adom

Texas Instruments Pre-ordered Products, HTSSOP-16(4.4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8428PPWPR

Texas Instruments · Pre-ordered Products · HTSSOP-16(4.4x5)

DRV8428PPWPR from Texas Instruments, in a HTSSOP-16(4.4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VM power_in Motor supply (4.2 V to 33 V recommended); bypass to PGND with a 0.01 µF ceramic capacitor rated for VM plus a bulk capacitor rated for VM.
2 PGND power_in Power ground; connect to system ground.
3 AOUT1 output Winding A output; connect to the motor winding.
4 AOUT2 output Winding A output; connect to the motor winding.
5 BOUT2 output Winding B output; connect to the motor winding.
6 BOUT1 output Winding B output; connect to the motor winding.
7 GND power_in Device ground; connect to system ground.
8 DVDD power_out Logic supply regulator output (nominally 5 V, up to 2 mA load); bypass to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V.
9 VREFB input Reference voltage input (0.05 V to 3 V); the voltage on this pin sets the full-scale chopping current in H-bridge B.
10 VREFA input Reference voltage input (0.05 V to 3 V); the voltage on this pin sets the full-scale chopping current in H-bridge A.
11 DECAY/TOFF input Seven-level pin that sets the decay mode and PWM off time (7, 16 or 32 µs).
12 BIN2 input Bridge B PWM input; logic controls the state of H-bridge B, internal pulldown.
13 BIN1 input Bridge B PWM input; logic controls the state of H-bridge B, internal pulldown.
14 AIN2 input PWM input for H-bridge A (datasheet text describes it as bridge B input); logic controls the bridge state, internal pulldown.
15 AIN1 input Bridge A PWM input; logic controls the state of H-bridge A, internal pulldown.
16 nSLEEP input Sleep mode input; logic high enables the device, logic low enters low-power sleep mode, internal pulldown; a low pulse clears faults and it must not be tied to DVDD.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16(4.4x5)
Category Solders / Accessories / Batteries
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VM operating supply voltage VVM 4.2 33 V 7
Logic input voltage VI 0 5.5 V 7
Reference rms voltage VREF 0.05 3 V VREFA, VREFB 7
Applied PWM frequency fPWM 0 100 kHz APH, AEN, BPH, BEN, AIN1, AIN2, BIN1, BIN2 7
Motor full-scale current IFS 0 1 A xOUTx 7
Motor rms current Irms 0 0.7 A xOUTx 7
Operating ambient temperature TA -40 125 °C 7
Operating junction temperature TJ -40 150 °C 7
Junction-to-ambient thermal resistance RθJA 46.4 °C/W PWP (HTSSOP) 16-pin 7
Junction-to-case (top) thermal resistance RθJC(top) 39.8 °C/W PWP (HTSSOP) 16-pin 7
Junction-to-board thermal resistance RθJB 19.9 °C/W PWP (HTSSOP) 16-pin 7
Junction-to-top characterization parameter ψJT 1.3 °C/W PWP (HTSSOP) 16-pin 7
Junction-to-board characterization parameter ψJB 19.9 °C/W PWP (HTSSOP) 16-pin 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 6.3 °C/W PWP (HTSSOP) 16-pin 7
VM operating supply current IVM 3.8 5.6 mA nSLEEP = 1, no motor load 8
VM sleep mode supply current IVMQ 2 4 µA nSLEEP = 0 8
Sleep time tSLEEP 120 µs nSLEEP = 0 to sleep mode 8
Wake-up time tWAKE 0.8 1.2 ms nSLEEP = 1 to output transition 8
Turn-on time tON 0.8 1.2 ms VM > UVLO to output transition 8
Internal regulator voltage VDVDD 4.5 5 5.5 V No external load, 6V < VVM < 33V 8
Internal regulator voltage VDVDD 3.9 4.05 V No external load, VVM = 4.2V 8
Input logic low voltage VIL 0 0.6 V 8
Input logic high voltage VIH 1.5 5.5 V 8
Input logic hysteresis VHYS 150 mV 8
Input logic low current IIL -1 1 µA VIN = 0V 8
Input logic high current IIH 100 µA VIN = 5V 8
Propagation delay tPD 750 ns xPH, xEN, xINx input to current change 8
Seven-level input voltage level 1 VI1 0 0.1 V Tied to GND 8
Seven-level input voltage level 2 VI2 0.2 0.35 V 14.7kΩ ± 1% to GND 8
Seven-level input voltage level 3 VI3 0.55 0.8 V 44.2kΩ ± 1% to GND 8
Seven-level input voltage level 4 VI4 1 1.25 V 100kΩ ± 1% to GND 8
Seven-level input voltage level 5 VI5 1.5 1.75 V 249kΩ ± 1% to GND 8
Seven-level input voltage level 6 VI6 2.1 2.4 V Hi-Z 8
Seven-level input voltage level 7 VI7 3 5.5 V Tied to DVDD 8
Output pull-up current IO 22.5 µA 8
High-side FET on-resistance RDS(ONH) 750 875 mΩ TJ = 25°C, IO = -0.5A 8
High-side FET on-resistance RDS(ONH) 1130 1350 mΩ TJ = 125°C, IO = -0.5A 8
High-side FET on-resistance RDS(ONH) 1250 1450 mΩ TJ = 150°C, IO = -0.5A 8
Low-side FET on-resistance RDS(ONL) 750 875 mΩ TJ = 25°C, IO = 0.5A 8
Low-side FET on-resistance RDS(ONL) 1130 1350 mΩ TJ = 125°C, IO = 0.5A 8
Low-side FET on-resistance RDS(ONL) 1250 1450 mΩ TJ = 150°C, IO = 0.5A 8
Output slew rate tSR 240 V/µs VM = 24V, IO = 0.5A, between 10% and 90% 8
Transimpedance gain KV 2.805 3 3.195 V/A VREF = 3V 8
PWM off-time, mixed 30% decay tOFF 7 µs DECAY/TOFF = 14.7kΩ to GND 8
PWM off-time, mixed 30% decay tOFF 16 µs DECAY/TOFF = 44.2kΩ to GND 8
PWM off-time, mixed 30% decay tOFF 32 µs DECAY/TOFF = 100kΩ to GND 8
PWM off-time, smart tune dynamic decay tOFF 7 µs DECAY/TOFF = 249kΩ to GND 8
PWM off-time, smart tune dynamic decay tOFF 16 µs DECAY/TOFF = Hi-Z 8
PWM off-time, smart tune dynamic decay tOFF 32 µs DECAY/TOFF = DVDD 8
Current trip accuracy ΔITRIP -15 15 % IO = 1A, 10% to 20% current setting 9
Current trip accuracy ΔITRIP -10 10 % IO = 1A, 20% to 67% current setting 9
Current trip accuracy ΔITRIP -6 6 % IO = 1A, 68% to 100% current setting 9
AOUT and BOUT current matching IO,CH -2.5 2.5 % IO = 1A 9
VM UVLO lockout, falling VUVLO 3.8 3.95 4.05 V VM falling, UVLO falling 9
VM UVLO lockout, rising VUVLO 3.9 4.05 4.15 V VM rising, UVLO rising 9
Undervoltage hysteresis VUVLO,HYS 100 mV Rising to falling threshold 9
Overcurrent protection IOCP 1.7 A Current through any FET 9
Overcurrent deglitch time tOCP 1.8 µs 9
Overcurrent retry time tRETRY 4 ms 9
Thermal shutdown TOTSD 150 165 180 °C Die temperature TJ 9
Thermal shutdown hysteresis THYS_OTSD 20 °C Die temperature TJ 9

CAD (KiCad official)

  • Symbol: DRV8428PPWPR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16(4.4x5) (KiCad packages3D, STEP)
  • 3D model files: drv8428ppwpr-etched.step / drv8428ppwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8428ppwpr.step / drv8428ppwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (52 pp, sha256 d522fe34b3f27f75, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF