component
DRV8428ERTER
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Texas Instruments Motor Driver ICs, WQFN-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8428ERTER
Texas Instruments · Motor Driver ICs · WQFN-16(3x3)
DRV8428ERTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 2 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 3 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 4 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 5 | GND | power_in | Device ground; connect to system ground. |
| 6 | DVDD | power_out | Internal logic regulator output, nominally 5 V and able to supply at most 2 mA; bypass to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 7 | VREFB | input | Reference voltage input that sets the full-scale chopping current of H-bridge B (IFS = VREFB / 3 V/A), with a specified VREF range of 0.05 V to 3 V. |
| 8 | VREFA | input | Reference voltage input that sets the full-scale chopping current of H-bridge A (IFS = VREFA / 3 V/A), with a specified VREF range of 0.05 V to 3 V. |
| 9 | DECAY/TOFF | input | Seven-level input that selects the decay mode and PWM off-time (7, 16 or 32 µs) through a resistor to GND, a high-impedance state, or a connection to DVDD, as listed in Table 7-4. |
| 10 | BPH | input | Bridge B phase input; a logic high drives current from BOUT1 to BOUT2, with logic input levels of 0 V to 5.5 V. |
| 11 | BEN | input | Bridge B enable input; a logic high enables bridge B and a logic low disables it into high impedance. |
| 12 | APH | input | Bridge A phase input; a logic high drives current from AOUT1 to AOUT2, with logic input levels of 0 V to 5.5 V. |
| 13 | AEN | input | Bridge A enable input; a logic high enables bridge A and a logic low disables it into high impedance. |
| 14 | nSLEEP | input | Sleep-mode input; a logic high enables the device, a logic low enters low-power sleep, it has an internal pull-down, and a low pulse clears faults. |
| 15 | VM | power_in | Motor supply input with a recommended operating range of 4.2 V to 33 V, bypassed to PGND with a 0.01 µF ceramic capacitor and a bulk capacitor rated for VM. |
| 16 | PGND | power_in | Power ground; connect to system ground. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VVM 可确保正常（直流）运行的电源电压范围 | VVM | 4.2 | 33 | V | 7 | ||
| 逻辑电平输入电压 | VI | 0 | 5.5 | V | 7 | ||
| 基准 rms 电压范围（VREFA、VREFB） | VREF | 0.05 | 3 | V | 7 | ||
| 施加的 PWM 信号频率（APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2） | ƒPWM | 0 | 100 | kHz | 7 | ||
| 电机满量程电流 (xOUTx) | IFS | 0 | 1 | A | 7 | ||
| 电机均方根电流 (xOUTx) | Irms | 0 | 0.7 | A | 7 | ||
| 工作环境温度 | TA | -40 | 125 | °C | 7 | ||
| 工作结温 | TJ | -40 | 150 | °C | 7 | ||
| VM 工作电源电流 | IVM | 3.8 | 5.6 | mA | nSLEEP = 1，无电机负载 | 8 | |
| VM 睡眠模式电源电流 | IVMQ | 2 | 4 | μA | nSLEEP = 0 | 8 | |
| 内部稳压器电压 | VDVDD | 4.5 | 5 | 5.5 | V | 无外部负载，6V < VVM < 33V | 8 |
| 内部稳压器电压 | VDVDD | 3.9 | 4.05 | V | 无外部负载，VVM = 4.2V | 8 | |
| 输入逻辑低电平电压 | VIL | 0 | 0.6 | V | 8 | ||
| 输入逻辑高电平电压 | VIH | 1.5 | 5.5 | V | 8 | ||
| 输入逻辑低电平电流 | IIL | -1 | 1 | μA | VIN = 0V | 8 | |
| 电压电平 1 | VI1 | 0 | 0.1 | V | 连接至 GND | 8 | |
| 电压电平 2 | VI2 | 0.2 | 0.35 | V | 14.7kΩ ± 1% 至 GND | 8 | |
| 电压电平 3 | VI3 | 0.55 | 0.8 | V | 44.2kΩ ± 1% 至 GND | 8 | |
| 电压电平 4 | VI4 | 1 | 1.25 | V | 100kΩ ± 1% 至 GND | 8 | |
| 电压电平 5 | VI5 | 1.5 | 1.75 | V | 249kΩ ± 1% 至 GND | 8 | |
| 电压电平 6 | VI6 | 2.1 | 2.4 | V | 高阻态 | 8 | |
| 电压电平 7 | VI7 | 3 | 5.5 | V | 连接至 DVDD | 8 | |
| 高侧 FET 导通电阻 | RDS(ONH) | 750 | 875 | mΩ | TJ = 25°C、IO = -0.5A | 8 | |
| 高侧 FET 导通电阻 | RDS(ONH) | 1130 | 1350 | mΩ | TJ = 125°C、IO = -0.5A | 8 | |
| 高侧 FET 导通电阻 | RDS(ONH) | 1250 | 1450 | mΩ | TJ = 150°C、IO = -0.5A | 8 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 750 | 875 | mΩ | TJ = 25°C、IO = 0.5A | 8 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 1130 | 1350 | mΩ | TJ = 125°C、IO = 0.5A | 8 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 1250 | 1450 | mΩ | TJ = 150°C、IO = 0.5A | 8 | |
| 跨阻增益 | KV | 2.805 | 3 | 3.195 | V/A | VREF = 3V | 8 |
| 电流跳变精度 | ΔITRIP | -15 | 15 | % | IO = 1A，10% 至 20% 电流设置 | 9 | |
| 电流跳变精度 | ΔITRIP | -10 | 10 | % | IO = 1A，20% 至 67% 电流设置 | 9 | |
| 电流跳变精度 | ΔITRIP | -6 | 6 | % | IO = 1A，68% 至 100% 电流设置 | 9 | |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | 2.5 | % | IO = 1A | 9 | |
| VM UVLO 锁定（下降） | VUVLO | 3.8 | 3.95 | 4.05 | V | VM 下降，UVLO 下降 | 9 |
| VM UVLO 锁定（上升） | VUVLO | 3.9 | 4.05 | 4.15 | V | VM 上升，UVLO 上升 | 9 |
| 热关断 | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 9 |
| 唤醒时间 | tWAKE | 0.8 | 1.2 | ms | nSLEEP = 1 至输出转换 | 8 | |
| 开通时间 | tON | 0.8 | 1.2 | ms | VM > UVLO 至输出转换 | 8 | |
| 结至环境热阻 RθJA（RTE 列） | RθJA | 47 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 结至外壳（顶部）热阻（RTE 列） | RθJC(top) | 46.1 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 结至电路板热阻（RTE 列） | RθJB | 19.9 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 结至顶部特征参数（RTE 列） | ψJT | 1.1 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 结至电路板特征参数（RTE 列） | ψJB | 19.8 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 结至外壳（底部）热阻（RTE 列） | RθJC(bot) | 8.5 | °C/W | RTE (WQFN) 16 引脚 | 7 | ||
| 休眠时间 | tSLEEP | 120 | μs | nSLEEP = 0 至睡眠模式 | 8 | ||
| 输入逻辑迟滞 | VHYS | 150 | mV | 8 | |||
| 输入逻辑高电平电流 | IIH | 100 | μA | VIN = 5V | 8 | ||
| 传播延迟 | tPD | 750 | ns | 通过 xPH、xEN、xINx 输入改变电流 | 8 | ||
| 输出上拉电流 | IO | 22.5 | μA | 8 | |||
| 输出压摆率 | tSR | 240 | V/µs | VM = 24V，IO = 0.5A，在 10% 至 90% 之间 | 8 | ||
| PWM 关断时间，混合 30% 衰减 | tOFF | 7 | μs | DECAY/TOFF = 14.7kΩ 至 GND | 8 | ||
| PWM 关断时间，混合 30% 衰减 | tOFF | 16 | μs | DECAY/TOFF = 44.2kΩ 至 GND | 8 | ||
| PWM 关断时间，混合 30% 衰减 | tOFF | 32 | μs | DECAY/TOFF = 100kΩ 至 GND | 8 | ||
| PWM 关断时间，智能调优动态衰减 | tOFF | 7 | μs | DECAY/TOFF = 249kΩ 至 GND | 8 | ||
| PWM 关断时间，智能调优动态衰减 | tOFF | 16 | μs | DECAY/TOFF = 高阻态 | 8 | ||
| PWM 关断时间，智能调优动态衰减 | tOFF | 32 | μs | DECAY/TOFF = DVDD | 8 | ||
| 欠压迟滞 | VUVLO,HYS | 100 | mV | 上升至下降阈值 | 9 | ||
| 过流保护 | IOCP | 1.7 | A | 流经任何 FET 的电流 | 9 | ||
| 过流抗尖峰时间 | tOCP | 1.8 | μs | 9 | |||
| 过流重试时间 | tRETRY | 4 | ms | 9 |
CAD (KiCad official)
- Symbol:
DRV8428ERTER - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
drv8428erter-etched.step/drv8428erter-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8428erter.step/drv8428erter.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
d522fe34b3f27f75, retrieved 2026-10-29, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8428ERTER
**Texas Instruments** · Motor Driver ICs · WQFN-16(3x3)
DRV8428ERTER from Texas Instruments, in a WQFN-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 2 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 3 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 4 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase-node voltage is limited to -1 V to VVM + 1 V. |
| 5 | GND | power_in | Device ground; connect to system ground. |
| 6 | DVDD | power_out | Internal logic regulator output, nominally 5 V and able to supply at most 2 mA; bypass to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 7 | VREFB | input | Reference voltage input that sets the full-scale chopping current of H-bridge B (IFS = VREFB / 3 V/A), with a specified VREF range of 0.05 V to 3 V. |
| 8 | VREFA | input | Reference voltage input that sets the full-scale chopping current of H-bridge A (IFS = VREFA / 3 V/A), with a specified VREF range of 0.05 V to 3 V. |
| 9 | DECAY/TOFF | input | Seven-level input that selects the decay mode and PWM off-time (7, 16 or 32 µs) through a resistor to GND, a high-impedance state, or a connection to DVDD, as listed in Table 7-4. |
| 10 | BPH | input | Bridge B phase input; a logic high drives current from BOUT1 to BOUT2, with logic input levels of 0 V to 5.5 V. |
| 11 | BEN | input | Bridge B enable input; a logic high enables bridge B and a logic low disables it into high impedance. |
| 12 | APH | input | Bridge A phase input; a logic high drives current from AOUT1 to AOUT2, with logic input levels of 0 V to 5.5 V. |
| 13 | AEN | input | Bridge A enable input; a logic high enables bridge A and a logic low disables it into high impedance. |
| 14 | nSLEEP | input | Sleep-mode input; a logic high enables the device, a logic low enters low-power sleep, it has an internal pull-down, and a low pulse clears faults. |
| 15 | VM | power_in | Motor supply input with a recommended operating range of 4.2 V to 33 V, bypassed to PGND with a 0.01 µF ceramic capacitor and a bulk capacitor rated for VM. |
| 16 | PGND | power_in | Power ground; connect to system ground. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-16(3x3) |
| Category | Power Supply Chip |
| Pins | 17 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VVM 可确保正常（直流）运行的电源电压范围 | VVM | 4.2 | | 33 | V | | 7 |
| 逻辑电平输入电压 | VI | 0 | | 5.5 | V | | 7 |
| 基准 rms 电压范围（VREFA、VREFB） | VREF | 0.05 | | 3 | V | | 7 |
| 施加的 PWM 信号频率（APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2） | ƒPWM | 0 | | 100 | kHz | | 7 |
| 电机满量程电流 (xOUTx) | IFS | 0 | | 1 | A | | 7 |
| 电机均方根电流 (xOUTx) | Irms | 0 | | 0.7 | A | | 7 |
| 工作环境温度 | TA | -40 | | 125 | °C | | 7 |
| 工作结温 | TJ | -40 | | 150 | °C | | 7 |
| VM 工作电源电流 | IVM | | 3.8 | 5.6 | mA | nSLEEP = 1，无电机负载 | 8 |
| VM 睡眠模式电源电流 | IVMQ | | 2 | 4 | μA | nSLEEP = 0 | 8 |
| 内部稳压器电压 | VDVDD | 4.5 | 5 | 5.5 | V | 无外部负载，6V < VVM < 33V | 8 |
| 内部稳压器电压 | VDVDD | 3.9 | | 4.05 | V | 无外部负载，VVM = 4.2V | 8 |
| 输入逻辑低电平电压 | VIL | 0 | | 0.6 | V | | 8 |
| 输入逻辑高电平电压 | VIH | 1.5 | | 5.5 | V | | 8 |
| 输入逻辑低电平电流 | IIL | -1 | | 1 | μA | VIN = 0V | 8 |
| 电压电平 1 | VI1 | 0 | | 0.1 | V | 连接至 GND | 8 |
| 电压电平 2 | VI2 | 0.2 | | 0.35 | V | 14.7kΩ ± 1% 至 GND | 8 |
| 电压电平 3 | VI3 | 0.55 | | 0.8 | V | 44.2kΩ ± 1% 至 GND | 8 |
| 电压电平 4 | VI4 | 1 | | 1.25 | V | 100kΩ ± 1% 至 GND | 8 |
| 电压电平 5 | VI5 | 1.5 | | 1.75 | V | 249kΩ ± 1% 至 GND | 8 |
| 电压电平 6 | VI6 | 2.1 | | 2.4 | V | 高阻态 | 8 |
| 电压电平 7 | VI7 | 3 | | 5.5 | V | 连接至 DVDD | 8 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 750 | 875 | mΩ | TJ = 25°C、IO = -0.5A | 8 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 1130 | 1350 | mΩ | TJ = 125°C、IO = -0.5A | 8 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 1250 | 1450 | mΩ | TJ = 150°C、IO = -0.5A | 8 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 750 | 875 | mΩ | TJ = 25°C、IO = 0.5A | 8 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 1130 | 1350 | mΩ | TJ = 125°C、IO = 0.5A | 8 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 1250 | 1450 | mΩ | TJ = 150°C、IO = 0.5A | 8 |
| 跨阻增益 | KV | 2.805 | 3 | 3.195 | V/A | VREF = 3V | 8 |
| 电流跳变精度 | ΔITRIP | -15 | | 15 | % | IO = 1A，10% 至 20% 电流设置 | 9 |
| 电流跳变精度 | ΔITRIP | -10 | | 10 | % | IO = 1A，20% 至 67% 电流设置 | 9 |
| 电流跳变精度 | ΔITRIP | -6 | | 6 | % | IO = 1A，68% 至 100% 电流设置 | 9 |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | | 2.5 | % | IO = 1A | 9 |
| VM UVLO 锁定（下降） | VUVLO | 3.8 | 3.95 | 4.05 | V | VM 下降，UVLO 下降 | 9 |
| VM UVLO 锁定（上升） | VUVLO | 3.9 | 4.05 | 4.15 | V | VM 上升，UVLO 上升 | 9 |
| 热关断 | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 9 |
| 唤醒时间 | tWAKE | | 0.8 | 1.2 | ms | nSLEEP = 1 至输出转换 | 8 |
| 开通时间 | tON | | 0.8 | 1.2 | ms | VM > UVLO 至输出转换 | 8 |
| 结至环境热阻 RθJA（RTE 列） | RθJA | | 47 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 结至外壳（顶部）热阻（RTE 列） | RθJC(top) | | 46.1 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 结至电路板热阻（RTE 列） | RθJB | | 19.9 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 结至顶部特征参数（RTE 列） | ψJT | | 1.1 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 结至电路板特征参数（RTE 列） | ψJB | | 19.8 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 结至外壳（底部）热阻（RTE 列） | RθJC(bot) | | 8.5 | | °C/W | RTE (WQFN) 16 引脚 | 7 |
| 休眠时间 | tSLEEP | | 120 | | μs | nSLEEP = 0 至睡眠模式 | 8 |
| 输入逻辑迟滞 | VHYS | | 150 | | mV | | 8 |
| 输入逻辑高电平电流 | IIH | | 100 | | μA | VIN = 5V | 8 |
| 传播延迟 | tPD | | 750 | | ns | 通过 xPH、xEN、xINx 输入改变电流 | 8 |
| 输出上拉电流 | IO | | 22.5 | | μA | | 8 |
| 输出压摆率 | tSR | | 240 | | V/µs | VM = 24V，IO = 0.5A，在 10% 至 90% 之间 | 8 |
| PWM 关断时间，混合 30% 衰减 | tOFF | | 7 | | μs | DECAY/TOFF = 14.7kΩ 至 GND | 8 |
| PWM 关断时间，混合 30% 衰减 | tOFF | | 16 | | μs | DECAY/TOFF = 44.2kΩ 至 GND | 8 |
| PWM 关断时间，混合 30% 衰减 | tOFF | | 32 | | μs | DECAY/TOFF = 100kΩ 至 GND | 8 |
| PWM 关断时间，智能调优动态衰减 | tOFF | | 7 | | μs | DECAY/TOFF = 249kΩ 至 GND | 8 |
| PWM 关断时间，智能调优动态衰减 | tOFF | | 16 | | μs | DECAY/TOFF = 高阻态 | 8 |
| PWM 关断时间，智能调优动态衰减 | tOFF | | 32 | | μs | DECAY/TOFF = DVDD | 8 |
| 欠压迟滞 | VUVLO,HYS | | 100 | | mV | 上升至下降阈值 | 9 |
| 过流保护 | IOCP | | 1.7 | | A | 流经任何 FET 的电流 | 9 |
| 过流抗尖峰时间 | tOCP | | 1.8 | | μs | | 9 |
| 过流重试时间 | tRETRY | | 4 | | ms | | 9 |
## CAD (KiCad official)
- Symbol: `DRV8428ERTER`
- Footprint: `Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm`
- 3D model: WQFN-16(3x3) (KiCad packages3D, STEP)
- 3D model files: `drv8428erter-etched.step` / `drv8428erter-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8428erter.step` / `drv8428erter.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8428e) (52 pp, sha256 `d522fe34b3f27f75`, retrieved 2026-10-29, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8428erter-datasheet.pdf)