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DRV8426PPWPR

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Texas Instruments Stepper Motor Driver, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8426PPWPR

Texas Instruments · Stepper Motor Driver · HTSSOP-28

DRV8426PPWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCP output Charge-pump output that must be bypassed to VM with a 0.22 µF, 16 V X7R ceramic capacitor.
2 VM power_in Motor supply pin, specified for 4.5 V to 33 V operation with absolute maximum 35 V, bypassed to PGND with 0.01 µF ceramic capacitors and a bulk capacitor rated for VM.
3 PGND power_in Power ground for the motor driver output stage, to be connected to system ground.
4 AOUT1 output Winding A output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
5 AOUT1 output Winding A output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
6 AOUT2 output Winding A output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
7 AOUT2 output Winding A output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
8 BOUT2 output Winding B output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
9 BOUT2 output Winding B output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
10 BOUT1 output Winding B output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
11 BOUT1 output Winding B output connected to the motor coil; continuous node voltage is limited to -1 V to VM + 1 V (100 ns transient -3 V to VM + 3 V).
12 PGND power_in Power ground for the motor driver output stage, to be connected to system ground.
13 VM power_in Motor supply pin, specified for 4.5 V to 33 V operation with absolute maximum 35 V, bypassed to PGND with 0.01 µF ceramic capacitors and a bulk capacitor rated for VM.
14 GND power_in Device ground, to be connected to system ground.
15 DVDD power_out Internal 5 V logic regulator output (4.75 V to 5.25 V with no external load) that can supply up to 2 mA and must be bypassed to GND with a 0.47 µF to 1 µF, 6.3 V or 10 V X7R capacitor.
16 nFAULT output Open-drain fault indicator that is pulled low during a fault and requires an external pull-up to 5 V, 3.3 V or 1.8 V (sink current limit 10 mA).
17 VREFB input Reference voltage input that sets the full-scale chopping current of H-bridge B (I_TRIP = VREF / 2.2 V/A), with a maximum of 3.3 V.
18 VREFA input Reference voltage input that sets the full-scale chopping current of H-bridge A (I_TRIP = VREF / 2.2 V/A), with a maximum of 3.3 V.
19 TOFF input Four-level input that sets the PWM off-time (0 = 7 µs, 1 = 16 µs, Hi-Z = 24 µs, 330 kΩ to GND = 32 µs) and the ripple current in smart-tune ripple control mode.
20 BDECAY input Four-level input that sets the decay mode for H-bridge B (0 = smart-tune dynamic decay, 1 = smart-tune ripple control, Hi-Z = mixed decay, 330 kΩ to GND = fast decay).
21 ADECAY input Four-level input that sets the decay mode for H-bridge A (0 = smart-tune dynamic decay, 1 = smart-tune ripple control, Hi-Z = mixed decay, 330 kΩ to GND = fast decay).
22 BIN2 input PWM input for H-bridge B that controls the bridge state, with an internal pull-down; logic inputs accept 0 to 5.5 V.
23 BIN1 input PWM input for H-bridge B that controls the bridge state, with an internal pull-down; logic inputs accept 0 to 5.5 V.
24 AIN2 input PWM input for H-bridge A that controls the bridge state, with an internal pull-down; logic inputs accept 0 to 5.5 V.
25 AIN1 input PWM input for H-bridge A that controls the bridge state, with an internal pull-down; logic inputs accept 0 to 5.5 V.
26 nSLEEP input Sleep-mode input where logic high enables the device and logic low enters low-power sleep (internal pull-down); a low pulse of 20 µs to 40 µs clears faults and nSLEEP must not be tied to DVDD.
27 CPL passive Charge-pump negative switch node, connected to CPH through a 0.022 µF X7R capacitor rated for VM.
28 CPH passive Charge-pump switch node, connected to CPL through a 0.022 µF X7R capacitor rated for VM.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28
Category Motor Driver ICs
Pins 29

CAD (KiCad official)

  • Symbol: DRV8426PPWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: drv8426ppwpr-etched.step / drv8426ppwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8426ppwpr.step / drv8426ppwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (54 pp, sha256 a28056b73354293f, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF