component
DRV8426EPWPR
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
2afcd00
DRV8426EPWPR
Texas Instruments · Motor Driver ICs · HTSSOP-28-EP
DRV8426EPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | output | Charge pump output; connect to VM through a low-ESR X7R 0.22µF 16V ceramic capacitor. |
| 2 | VM | power_in | Motor supply input, 4.5 V to 33 V for normal DC operation; bypass to PGND with 0.01µF ceramic capacitors and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground; connect to system ground. |
| 4 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 5 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 6 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 7 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 8 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 9 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 10 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 11 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 12 | PGND | power_in | Power ground; connect to system ground. |
| 13 | VM | power_in | Motor supply input, 4.5 V to 33 V for normal DC operation; bypass to PGND with 0.01µF ceramic capacitors and a bulk capacitor rated for VM. |
| 14 | GND | power_in | Device ground; connect to system ground. |
| 15 | DVDD | power_out | Internal 5 V logic regulator output (nominal, supplies up to 2 mA); bypass to GND with a 0.47µF to 1µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 16 | nFAULT | output | Open-drain fault indicator, pulled low during a fault; requires an external pull-up and sinks up to 10 mA. |
| 17 | VREFB | input | Reference voltage input that sets the full-scale chopping current of H-bridge B; recommended range 0.05 V to 3.3 V. |
| 18 | VREFA | input | Reference voltage input that sets the full-scale chopping current of H-bridge A; recommended range 0.05 V to 3.3 V. |
| 19 | TOFF | input | Four-level input that sets the PWM current-chopping off-time to 7, 16, 24 or 32 µs. |
| 20 | BDECAY | input | Four-level input that sets the decay mode of H-bridge B. |
| 21 | ADECAY | input | Four-level input that sets the decay mode of H-bridge A. |
| 22 | BPH | input | Bridge B phase input; logic high drives current from BOUT1 to BOUT2. |
| 23 | BEN | input | Bridge B enable input; logic high enables bridge B, logic low disables it to high impedance. |
| 24 | APH | input | Bridge A phase input; logic high drives current from AOUT1 to AOUT2. |
| 25 | AEN | input | Bridge A enable input; logic high enables bridge A, logic low disables it to high impedance. |
| 26 | nSLEEP | input | Sleep mode input; logic high enables the device, logic low enters low-power sleep, internal pull-down, and a low pulse clears faults. |
| 27 | CPL | passive | Charge pump negative switch node; connect a low-ESR X7R 0.022µF ceramic capacitor rated VM between CPH and CPL. |
| 28 | CPH | passive | Charge pump switch node; connect a low-ESR X7R 0.022µF ceramic capacitor rated VM between CPH and CPL. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Power Supply Chip |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VM 工作电源电流 | IVM | 5 | 6.5 | mA | nSLEEP = 1，无电机负载 | 9 | |
| VM 休眠模式电源电流 | IVMQ | 2 | 4 | μA | nSLEEP = 0 | 9 | |
| 休眠时间 | tSLEEP | 120 | μs | nSLEEP = 0 至休眠模式 | 9 | ||
| nSLEEP 复位脉冲 | tRESET | 20 | 40 | μs | nSLEEP 低电平至清除故障 | 9 | |
| 唤醒时间 | tWAKE | 0.8 | 1.2 | ms | nSLEEP = 1 至输出转换 | 9 | |
| 开通时间 | tON | 0.8 | 1.2 | ms | VM > UVLO 至输出转换 | 9 | |
| 内部稳压器电压 | VDVDD | 4.75 | 5 | 5.25 | V | 无外部负载，6V < VVM < 33V | 9 |
| 内部稳压器电压 | VDVDD | 4.2 | 4.35 | V | 无外部负载，VVM = 4.5V | 9 | |
| 电荷泵开关频率 | f(VCP) | 360 | kHz | VVM > UVLO；nSLEEP = 1 | 9 | ||
| 输入逻辑低电平电压 | VIL | 0 | 0.6 | V | 9 | ||
| 输入逻辑高电平电压 | VIH | 1.5 | 5.5 | V | 9 | ||
| 输入逻辑迟滞 | VHYS | 150 | mV | 9 | |||
| 输入逻辑低电平电流 | IIL | -1 | 1 | μA | VIN = 0V | 9 | |
| 输入逻辑高电平电流 | IIH | 100 | μA | VIN = 5V | 9 | ||
| 传播延迟 | tPD | 800 | ns | 从 xPH、xEN、xINx 输入到电流改变 | 9 | ||
| 输入逻辑低电平电压 (连接至 GND) | VI1 | 0 | 0.6 | V | 连接至 GND | 9 | |
| 四电平输入 330kΩ 电压 | VI2 | 1 | 1.25 | 1.4 | V | 330kΩ ± 5% 至 GND | 9 |
| 输入高阻态电压 | VI3 | 1.8 | 2 | 2.2 | V | 高阻态（>500kΩ 至 GND） | 9 |
| 输入逻辑高电平电压 (连接至 DVDD) | VI4 | 2.7 | 5.5 | V | 连接至 DVDD | 9 | |
| 输出上拉电流 | IO | 10 | μA | 9 | |||
| 输出逻辑低电平电压 | VOL | 0.5 | V | IO = 5mA | 9 | ||
| 输出逻辑高电平泄漏电流 | IOH | -1 | 1 | μA | 9 | ||
| 高侧 FET 导通电阻 | RDS(ONH) | 450 | 550 | mΩ | TJ = 25°C、IO = -1A | 9 | |
| 高侧 FET 导通电阻 | RDS(ONH) | 700 | 850 | mΩ | TJ = 125°C、IO = -1A | 9 | |
| 高侧 FET 导通电阻 | RDS(ONH) | 780 | 950 | mΩ | TJ = 150°C、IO = -1A | 9 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 450 | 550 | mΩ | TJ = 25°C、IO = 1A | 9 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 700 | 850 | mΩ | TJ = 125°C、IO = 1A | 9 | |
| 低侧 FET 导通电阻 | RDS(ONL) | 780 | 950 | mΩ | TJ = 150°C、IO = 1A | 9 | |
| 输出压摆率 | tSR | 240 | V/µs | VM = 24V，IO = 1A，在 10% 至 90% 之间 | 9 | ||
| 跨阻增益 | KV | 2.09 | 2.2 | 2.31 | V/A | VREF = 3.3V | 9 |
| VREF 泄漏电流 | IVREF | 8.25 | μA | VREF = 3.3V | 9 | ||
| PWM 关断时间 | tOFF | 7 | μs | TOFF = 0 | 10 | ||
| PWM 关断时间 | tOFF | 16 | μs | TOFF = 1 | 10 | ||
| PWM 关断时间 | tOFF | 24 | μs | TOFF =高阻态 | 10 | ||
| PWM 关断时间 | tOFF | 32 | μs | TOFF = 330kΩ 至 GND | 10 | ||
| 电流跳变精度 | ΔITRIP | -15 | 15 | % | IO = 1.5A，10% 至 20% 电流设置 | 10 | |
| 电流跳变精度 | ΔITRIP | -10 | 10 | % | IO = 1.5A，20% 至 67% 电流设置 | 10 | |
| 电流跳变精度 | ΔITRIP | -5 | 5 | % | IO = 1.5A，68% 至 100% 电流设置 | 10 | |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | 2.5 | % | IO = 1.5A | 10 | |
| VM UVLO 锁定 (VM 下降) | VUVLO | 4.1 | 4.25 | 4.35 | V | VM 下降，UVLO 下降 | 10 |
| VM UVLO 锁定 (VM 上升) | VUVLO | 4.2 | 4.35 | 4.45 | V | VM 上升，UVLO 上升 | 10 |
| 欠压迟滞 | VUVLO,HYS | 100 | mV | 上升至下降阈值 | 10 | ||
| 过流保护 | IOCP | 2.5 | A | 流经任何 FET 的电流 | 10 | ||
| 过流抗尖峰时间 | tOCP | 1.8 | μs | 10 | |||
| 热关断 | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 10 |
| 热关断迟滞 | THYS_OTSD | 20 | °C | 内核温度 TJ | 10 | ||
| 电源电压范围 (直流运行) | VVM | 4.5 | 33 | V | 可确保正常（直流）运行的电源电压范围 | 8 | |
| 逻辑电平输入电压 | VI | 0 | 5.5 | V | 8 | ||
| 基准 rms 电压范围 | VREF | 0.05 | 3.3 | V | VREFA、VREFB | 8 | |
| 施加的 PWM 信号频率 | ƒPWM | 0 | 100 | kHz | APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2 | 8 | |
| 电机满量程电流 | IFS | 0 | 1.5 | A | xOUTx | 8 | |
| 电机均方根电流 | Irms | 0 | 1.1 | A | xOUTx | 8 | |
| 工作环境温度 | TA | -40 | 125 | °C | 8 | ||
| 工作结温 | TJ | -40 | 150 | °C | 8 | ||
| 结至环境热阻 (HTSSOP 28 引脚) | RθJA | 33 | °C/W | PWP (HTSSOP) 28 引脚 | 8 | ||
| 结至外壳（顶部）热阻 (HTSSOP 28 引脚) | RθJC(top) | 28 | °C/W | PWP (HTSSOP) 28 引脚 | 8 | ||
| 结至电路板热阻 (HTSSOP 28 引脚) | RθJB | 12.9 | °C/W | PWP (HTSSOP) 28 引脚 | 8 | ||
| 结至顶部特征参数 (HTSSOP 28 引脚) | ψJT | 0.7 | °C/W | PWP (HTSSOP) 28 引脚 | 8 | ||
| 结至电路板特征参数 (HTSSOP 28 引脚) | ψJB | 12.8 | °C/W | PWP (HTSSOP) 28 引脚 | 8 | ||
| 结至外壳（底部）热阻 (HTSSOP 28 引脚) | RθJC(bot) | 4.9 | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
CAD (KiCad official)
- Symbol:
DRV8426EPWPR - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
drv8426epwpr-etched.step/drv8426epwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8426epwpr.step/drv8426epwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (54 pp, sha256
5b89b7592cb06a0c, retrieved 2026-10-28, tier: manufacturer) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8426EPWPR
**Texas Instruments** · Motor Driver ICs · HTSSOP-28-EP
DRV8426EPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | output | Charge pump output; connect to VM through a low-ESR X7R 0.22µF 16V ceramic capacitor. |
| 2 | VM | power_in | Motor supply input, 4.5 V to 33 V for normal DC operation; bypass to PGND with 0.01µF ceramic capacitors and a bulk capacitor rated for VM. |
| 3 | PGND | power_in | Power ground; connect to system ground. |
| 4 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 5 | AOUT1 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 6 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 7 | AOUT2 | output | Winding A output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 8 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 9 | BOUT2 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 10 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 11 | BOUT1 | output | Winding B output connected to the motor winding; continuous phase node voltage limited to -1 V to VM + 1 V. |
| 12 | PGND | power_in | Power ground; connect to system ground. |
| 13 | VM | power_in | Motor supply input, 4.5 V to 33 V for normal DC operation; bypass to PGND with 0.01µF ceramic capacitors and a bulk capacitor rated for VM. |
| 14 | GND | power_in | Device ground; connect to system ground. |
| 15 | DVDD | power_out | Internal 5 V logic regulator output (nominal, supplies up to 2 mA); bypass to GND with a 0.47µF to 1µF X7R ceramic capacitor rated 6.3 V or 10 V. |
| 16 | nFAULT | output | Open-drain fault indicator, pulled low during a fault; requires an external pull-up and sinks up to 10 mA. |
| 17 | VREFB | input | Reference voltage input that sets the full-scale chopping current of H-bridge B; recommended range 0.05 V to 3.3 V. |
| 18 | VREFA | input | Reference voltage input that sets the full-scale chopping current of H-bridge A; recommended range 0.05 V to 3.3 V. |
| 19 | TOFF | input | Four-level input that sets the PWM current-chopping off-time to 7, 16, 24 or 32 µs. |
| 20 | BDECAY | input | Four-level input that sets the decay mode of H-bridge B. |
| 21 | ADECAY | input | Four-level input that sets the decay mode of H-bridge A. |
| 22 | BPH | input | Bridge B phase input; logic high drives current from BOUT1 to BOUT2. |
| 23 | BEN | input | Bridge B enable input; logic high enables bridge B, logic low disables it to high impedance. |
| 24 | APH | input | Bridge A phase input; logic high drives current from AOUT1 to AOUT2. |
| 25 | AEN | input | Bridge A enable input; logic high enables bridge A, logic low disables it to high impedance. |
| 26 | nSLEEP | input | Sleep mode input; logic high enables the device, logic low enters low-power sleep, internal pull-down, and a low pulse clears faults. |
| 27 | CPL | passive | Charge pump negative switch node; connect a low-ESR X7R 0.022µF ceramic capacitor rated VM between CPH and CPL. |
| 28 | CPH | passive | Charge pump switch node; connect a low-ESR X7R 0.022µF ceramic capacitor rated VM between CPH and CPL. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Power Supply Chip |
| Pins | 29 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VM 工作电源电流 | IVM | | 5 | 6.5 | mA | nSLEEP = 1，无电机负载 | 9 |
| VM 休眠模式电源电流 | IVMQ | | 2 | 4 | μA | nSLEEP = 0 | 9 |
| 休眠时间 | tSLEEP | | 120 | | μs | nSLEEP = 0 至休眠模式 | 9 |
| nSLEEP 复位脉冲 | tRESET | 20 | | 40 | μs | nSLEEP 低电平至清除故障 | 9 |
| 唤醒时间 | tWAKE | 0.8 | | 1.2 | ms | nSLEEP = 1 至输出转换 | 9 |
| 开通时间 | tON | 0.8 | | 1.2 | ms | VM > UVLO 至输出转换 | 9 |
| 内部稳压器电压 | VDVDD | 4.75 | 5 | 5.25 | V | 无外部负载，6V < VVM < 33V | 9 |
| 内部稳压器电压 | VDVDD | 4.2 | | 4.35 | V | 无外部负载，VVM = 4.5V | 9 |
| 电荷泵开关频率 | f(VCP) | | 360 | | kHz | VVM > UVLO；nSLEEP = 1 | 9 |
| 输入逻辑低电平电压 | VIL | 0 | | 0.6 | V | | 9 |
| 输入逻辑高电平电压 | VIH | 1.5 | | 5.5 | V | | 9 |
| 输入逻辑迟滞 | VHYS | | 150 | | mV | | 9 |
| 输入逻辑低电平电流 | IIL | -1 | | 1 | μA | VIN = 0V | 9 |
| 输入逻辑高电平电流 | IIH | | | 100 | μA | VIN = 5V | 9 |
| 传播延迟 | tPD | | 800 | | ns | 从 xPH、xEN、xINx 输入到电流改变 | 9 |
| 输入逻辑低电平电压 (连接至 GND) | VI1 | 0 | | 0.6 | V | 连接至 GND | 9 |
| 四电平输入 330kΩ 电压 | VI2 | 1 | 1.25 | 1.4 | V | 330kΩ ± 5% 至 GND | 9 |
| 输入高阻态电压 | VI3 | 1.8 | 2 | 2.2 | V | 高阻态（>500kΩ 至 GND） | 9 |
| 输入逻辑高电平电压 (连接至 DVDD) | VI4 | 2.7 | | 5.5 | V | 连接至 DVDD | 9 |
| 输出上拉电流 | IO | | 10 | | μA | | 9 |
| 输出逻辑低电平电压 | VOL | | | 0.5 | V | IO = 5mA | 9 |
| 输出逻辑高电平泄漏电流 | IOH | -1 | | 1 | μA | | 9 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 450 | 550 | mΩ | TJ = 25°C、IO = -1A | 9 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 700 | 850 | mΩ | TJ = 125°C、IO = -1A | 9 |
| 高侧 FET 导通电阻 | RDS(ONH) | | 780 | 950 | mΩ | TJ = 150°C、IO = -1A | 9 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 450 | 550 | mΩ | TJ = 25°C、IO = 1A | 9 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 700 | 850 | mΩ | TJ = 125°C、IO = 1A | 9 |
| 低侧 FET 导通电阻 | RDS(ONL) | | 780 | 950 | mΩ | TJ = 150°C、IO = 1A | 9 |
| 输出压摆率 | tSR | | 240 | | V/µs | VM = 24V，IO = 1A，在 10% 至 90% 之间 | 9 |
| 跨阻增益 | KV | 2.09 | 2.2 | 2.31 | V/A | VREF = 3.3V | 9 |
| VREF 泄漏电流 | IVREF | | 8.25 | | μA | VREF = 3.3V | 9 |
| PWM 关断时间 | tOFF | | 7 | | μs | TOFF = 0 | 10 |
| PWM 关断时间 | tOFF | | 16 | | μs | TOFF = 1 | 10 |
| PWM 关断时间 | tOFF | | 24 | | μs | TOFF =高阻态 | 10 |
| PWM 关断时间 | tOFF | | 32 | | μs | TOFF = 330kΩ 至 GND | 10 |
| 电流跳变精度 | ΔITRIP | -15 | | 15 | % | IO = 1.5A，10% 至 20% 电流设置 | 10 |
| 电流跳变精度 | ΔITRIP | -10 | | 10 | % | IO = 1.5A，20% 至 67% 电流设置 | 10 |
| 电流跳变精度 | ΔITRIP | -5 | | 5 | % | IO = 1.5A，68% 至 100% 电流设置 | 10 |
| AOUT 和 BOUT 电流匹配 | IO,CH | -2.5 | | 2.5 | % | IO = 1.5A | 10 |
| VM UVLO 锁定 (VM 下降) | VUVLO | 4.1 | 4.25 | 4.35 | V | VM 下降，UVLO 下降 | 10 |
| VM UVLO 锁定 (VM 上升) | VUVLO | 4.2 | 4.35 | 4.45 | V | VM 上升，UVLO 上升 | 10 |
| 欠压迟滞 | VUVLO,HYS | | 100 | | mV | 上升至下降阈值 | 10 |
| 过流保护 | IOCP | | 2.5 | | A | 流经任何 FET 的电流 | 10 |
| 过流抗尖峰时间 | tOCP | | 1.8 | | μs | | 10 |
| 热关断 | TOTSD | 150 | 165 | 180 | °C | 内核温度 TJ | 10 |
| 热关断迟滞 | THYS_OTSD | | 20 | | °C | 内核温度 TJ | 10 |
| 电源电压范围 (直流运行) | VVM | 4.5 | | 33 | V | 可确保正常（直流）运行的电源电压范围 | 8 |
| 逻辑电平输入电压 | VI | 0 | | 5.5 | V | | 8 |
| 基准 rms 电压范围 | VREF | 0.05 | | 3.3 | V | VREFA、VREFB | 8 |
| 施加的 PWM 信号频率 | ƒPWM | 0 | | 100 | kHz | APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2 | 8 |
| 电机满量程电流 | IFS | 0 | | 1.5 | A | xOUTx | 8 |
| 电机均方根电流 | Irms | 0 | | 1.1 | A | xOUTx | 8 |
| 工作环境温度 | TA | -40 | | 125 | °C | | 8 |
| 工作结温 | TJ | -40 | | 150 | °C | | 8 |
| 结至环境热阻 (HTSSOP 28 引脚) | RθJA | | 33 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
| 结至外壳（顶部）热阻 (HTSSOP 28 引脚) | RθJC(top) | | 28 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
| 结至电路板热阻 (HTSSOP 28 引脚) | RθJB | | 12.9 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
| 结至顶部特征参数 (HTSSOP 28 引脚) | ψJT | | 0.7 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
| 结至电路板特征参数 (HTSSOP 28 引脚) | ψJB | | 12.8 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
| 结至外壳（底部）热阻 (HTSSOP 28 引脚) | RθJC(bot) | | 4.9 | | °C/W | PWP (HTSSOP) 28 引脚 | 8 |
## CAD (KiCad official)
- Symbol: `DRV8426EPWPR`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `drv8426epwpr-etched.step` / `drv8426epwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8426epwpr.step` / `drv8426epwpr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8426epwpr.pdf) (54 pp, sha256 `5b89b7592cb06a0c`, retrieved 2026-10-28, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8426epwpr-datasheet.pdf)