DRV8424PRGER from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VM	power_in	Motor supply voltage input, specified for 4.5 V to 33 V with a 35 V absolute maximum, and bypassed to PGND with a 0.01 µF ceramic capacitor per pin plus a bulk capacitor.
2	PGND	power_in	Power ground that must be connected to system ground.
3	AOUT1	output	Winding A output that connects to the motor winding.
4	AOUT2	output	Winding A output that connects to the motor winding.
5	BOUT2	output	Winding B output that connects to the motor winding.
6	BOUT1	output	Winding B output that connects to the motor winding.
7	PGND	power_in	Power ground that must be connected to system ground.
8	VM	power_in	Motor supply voltage input, specified for 4.5 V to 33 V with a 35 V absolute maximum, and bypassed to PGND with a 0.01 µF ceramic capacitor per pin plus a bulk capacitor.
9	GND	power_in	Device ground that must be connected to system ground.
10	DVDD	power_out	Internal logic regulator output with a nominal 5 V, which can supply up to 2 mA and must be bypassed to GND with a 0.47 µF to 1 µF X7R ceramic capacitor rated 6.3 V or 10 V.
11	nFAULT	output	Open-drain fault indicator that is driven low during a fault and requires an external pull-up resistor, with a sink current limit of 10 mA.
12	VREFB	input	Reference voltage input that sets the full-scale chopping current of H-bridge B, specified at 0.05 V to 3.3 V RMS for the DRV8424P.
13	VREFA	input	Reference voltage input that sets the full-scale chopping current of H-bridge A, specified at 0.05 V to 3.3 V RMS for the DRV8424P.
14	TOFF	input	Four-level input that sets the PWM current-chopping off time to 7 µs, 16 µs, 24 µs, or 32 µs, and also sets the ripple current in smart-tune ripple control mode.
15	BDECAY	input	Four-level input that sets the decay mode of H-bridge B.
16	ADECAY	input	Four-level input that sets the decay mode of H-bridge A.
17	BIN2	input	PWM logic input 2 for H-bridge B with an internal pull-down, where logic inputs accept 0 V to 5.5 V with VIH of 1.5 V minimum and VIL of 0.6 V maximum.
18	BIN1	input	PWM logic input 1 for H-bridge B with an internal pull-down, where logic inputs accept 0 V to 5.5 V with VIH of 1.5 V minimum and VIL of 0.6 V maximum.
19	AIN2	input	PWM logic input 2 with an internal pull-down, where logic inputs accept 0 V to 5.5 V with VIH of 1.5 V minimum and VIL of 0.6 V maximum.
20	AIN1	input	PWM logic input 1 for H-bridge A with an internal pull-down, where logic inputs accept 0 V to 5.5 V with VIH of 1.5 V minimum and VIL of 0.6 V maximum.
21	nSLEEP	input	Sleep-mode input where logic high enables the device and logic low enters low-power sleep, with an internal pull-down, and a low pulse clears faults.
22	CPL	passive	Charge pump negative switching node, connected to CPH through a 0.022 µF X7R ceramic capacitor rated for VM.
23	CPH	passive	Charge pump switching node, connected to CPL through a 0.022 µF X7R ceramic capacitor rated for VM.
24	VCP	power_out	Charge pump output, connected to VM through a 0.22 µF 16 V X7R ceramic capacitor.
25	PAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VQFN-24-EP(4x4)
Category	Motor Driver ICs
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
电源电压 (VM)	VM	-0.3		35	V		7
电荷泵电压（VCP、CPH）	VCP, CPH	-0.3			V		7
电荷泵负开关引脚 (CPL)	CPL	-0.3			V		7
nSLEEP 引脚电压	nSLEEP	-0.3			V		7
内部稳压器电压 (DVDD)	DVDD	-0.3		5.75	V		7
控制引脚电压（APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2、nFAULT、ADECAY、BDECAY、TOFF）		-0.3		5.75	V		7
开漏输出电流 (nFAULT)		0		10	mA		7
基准输入引脚电压（VREFA、VREFB）	VREFA, VREFB	-0.3		5.75	V		7
连续相节点引脚电压（AOUT1、AOUT2、BOUT1、BOUT2）	AOUT1, AOUT2, BOUT1, BOUT2	-1			V	连续	7
瞬态 100ns 相节点引脚电压（AOUT1、AOUT2、BOUT1、BOUT2）	AOUT1, AOUT2, BOUT1, BOUT2	-3			V	瞬态 100ns	7
工作环境温度 TA	TA	-40		125	°C		7
运行结温 TJ	TJ	-40		150	°C		7
贮存温度 Tstg	Tstg	-65		150	°C		7
静电放电人体放电模型 (HBM)	V(ESD)	-2000		2000	V	HBM，ANSI/ESDA/JEDEC JS-001	7
静电放电充电器件模型 (CDM) 其他引脚	V(ESD)	-500		500	V	CDM，JEDEC JESD22-C101，其他引脚	7
VVM 可确保正常（直流）运行的电源电压范围	VVM	4.5		33	V		8
逻辑电平输入电压	VI	0		5.5	V		8
基准均方根电压范围（VREFA、VREFB）（DRV8424P）	VREF	0.05		3.3	V		8
施加的 PWM 信号频率（APH、AEN、BPH、BEN、AIN1、AIN2、BIN1、BIN2）	ƒPWM	0		100	kHz		8
电机满量程电流 (xOUTx)（DRV8424P）	IFS	0		2.5	A		8
电机均方根电流 (xOUTx)（DRV8424P）	Irms	0		1.8	A		8
工作环境温度 TA（推荐）	TA	-40		125	°C		8
工作结温 TJ（推荐）	TJ	-40		150	°C		8
VM 工作电源电流	IVM		5	6.5	mA	nSLEEP = 1，无电机负载	9
VM 休眠模式电源电流	IVMQ		2	4	μA	nSLEEP = 0	9
nSLEEP 复位脉冲	tRESET	20		40	μs	nSLEEP 低电平至清除故障	9
唤醒时间	tWAKE	0.8		1.2	ms	nSLEEP = 1 至输出转换	9
开通时间	tON	0.8		1.2	ms	VM > UVLO 至输出转换	9
内部稳压器电压 (DVDD)，6V < VVM < 33V	VDVDD	4.75	5	5.25	V	无外部负载，6V < VVM < 33V	9
内部稳压器电压 (DVDD)，VVM = 4.5V	VDVDD	4.2		4.35	V	无外部负载，VVM = 4.5V	9
输入逻辑低电平电压	VIL	0		0.6	V		9
输入逻辑高电平电压	VIH	1.5		5.5	V		9
输入逻辑低电平电流	IIL	-1		1	μA	VIN = 0V	9
四电平输入逻辑低电平电压 (ADECAY、BDECAY、TOFF)	VI1	0		0.6	V	连接至 GND	9
四电平输入 330kΩ 至 GND 电压 (ADECAY、BDECAY、TOFF)	VI2	1	1.25	1.4	V	330kΩ ± 5% 至 GND	9
四电平输入高阻抗电压 (ADECAY、BDECAY、TOFF)	VI3	1.8	2	2.2	V	高阻抗（>500kΩ 至 GND）	9
四电平输入逻辑高电平电压 (ADECAY、BDECAY、TOFF)	VI4	2.7		5.5	V	连接至 DVDD	9
输出逻辑低电平电压 (nFAULT)	VOL			0.5	V	IO = 5mA	9
输出逻辑高电平泄漏电流 (nFAULT)	IOH	-1		1	μA		9
高侧 FET 导通电阻（DRV8424P）	RDS(ONH)		165	200	mΩ	TJ = 25°C、IO = -1A	9
低侧 FET 导通电阻（DRV8424P）	RDS(ONL)		165	200	mΩ	TJ = 25°C、IO = 1A	9
高侧 FET 导通电阻（DRV8424P）	RDS(ONH)		250	300	mΩ	TJ = 125°C、IO = -1A	9
低侧 FET 导通电阻（DRV8424P）	RDS(ONL)		250	300	mΩ	TJ = 125°C、IO = 1A	9
高侧 FET 导通电阻（DRV8424P）	RDS(ONH)		280	350	mΩ	TJ = 150°C、IO = -1A	9
低侧 FET 导通电阻（DRV8424P）	RDS(ONL)		280	350	mΩ	TJ = 150°C、IO = 1A	9
跨阻增益 KV	KV	1.254	1.32	1.386	V/A	VREF = 3.3V	10
电流跳变精度 10% 至 20% 电流设置	ΔITRIP	-8		12	%	IO = 2.5A，10% 至 20% 电流设置	10
电流跳变精度 20% 至 40% 电流设置	ΔITRIP	-7		7	%	IO = 2.5A，20% 至 40% 电流设置	10
电流跳变精度 40% 至 100% 电流设置	ΔITRIP	-5		5	%	IO = 2.5A，40% 至 100% 电流设置	10
AOUT 和 BOUT 电流匹配	IO,CH	-2.5		2.5	%	IO = 2.5A	10
VM UVLO 锁定（VM 下降，UVLO 下降）	VUVLO	4.1	4.25	4.35	V	VM 下降，UVLO 下降	10
VM UVLO 锁定（VM 上升，UVLO 上升）	VUVLO	4.2	4.35	4.45	V	VM 上升，UVLO 上升	10
热关断内核温度 TJ	TOTSD	150	165	180	°C	内核温度 TJ	10
结至环境热阻 (RθJA)	RθJA		40.7		°C/W	RGE (VQFN) 24 引脚	8
结至外壳（顶部）热阻 (RθJC(top))	RθJC(top)		31.8		°C/W	RGE (VQFN) 24 引脚	8
结至电路板热阻 (RθJB)	RθJB		17.7		°C/W	RGE (VQFN) 24 引脚	8
结至顶部特征参数 (ψJT)	ψJT		0.6		°C/W	RGE (VQFN) 24 引脚	8
结至电路板特征参数 (ψJB)	ψJB		17.7		°C/W	RGE (VQFN) 24 引脚	8
结至外壳（底部）热阻 (RθJC(bot))	RθJC(bot)		4.7		°C/W	RGE (VQFN) 24 引脚	8

CAD (KiCad official)

Symbol: DRV8424PRGER
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
3D model files: drv8424prger-etched.step / drv8424prger-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8424prger.step / drv8424prger.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (53 pp, sha256 61208cc09b733204, retrieved 2026-11-10, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DRV8424PRGER

Verified DRV8424PRGER

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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