component
DRV8424EPWPR
Public Made by Adomby adom
Texas Instruments Stepper Motor Driver, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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page.json+12−9@@ -53,13 +53,13 @@ "number": "1", "name": "VCP", "type": "power_out",- "description": "Charge pump output; connect 0.22\u00b5F 16V ceramic capacitor to VM for high-side gate driver power."+ "description": "Charge pump output; connect 0.22µF 16V ceramic capacitor to VM for high-side gate driver power." }, { "number": "2", "name": "VM", "type": "power_in",- "description": "Motor power supply (4.5-33V); bypass each pin with 0.01\u00b5F ceramic capacitor and bulk capacitor to PGND per section 9."+ "description": "Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9." }, { "number": "3",@@ -125,7 +125,7 @@ "number": "13", "name": "VM", "type": "power_in",- "description": "Motor power supply (4.5-33V); bypass each pin with 0.01\u00b5F ceramic capacitor and bulk capacitor to PGND per section 9."+ "description": "Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9." }, { "number": "14",@@ -137,7 +137,7 @@ "number": "15", "name": "DVDD", "type": "power_in",- "description": "Logic supply voltage (4.75-5.25V typical, section 6.5); bypass with 0.47-1\u00b5F X7R ceramic capacitor rated 6.3V or 10V."+ "description": "Logic supply voltage (4.75-5.25V typical, section 6.5); bypass with 0.47-1µF X7R ceramic capacitor rated 6.3V or 10V." }, { "number": "16",@@ -161,7 +161,7 @@ "number": "19", "name": "TOFF", "type": "input",- "description": "PWM turn-off time selection (four-level pin): 7\u00b5s (GND), 16\u00b5s (DVDD), 24\u00b5s (high impedance), or 32\u00b5s (330k\u03a9 to GND) per table 7-4 page 19."+ "description": "PWM turn-off time selection (four-level pin): 7µs (GND), 16µs (DVDD), 24µs (high impedance), or 32µs (330kΩ to GND) per table 7-4 page 19." }, { "number": "20",@@ -203,19 +203,19 @@ "number": "26", "name": "nSLEEP", "type": "input",- "description": "Sleep mode control input (internal 200k\u03a9 pull-down); logic high enables device; logic low enters low-power sleep mode (2\u00b5A per page 10); pulse clears fault latches per section 7.4.3."+ "description": "Sleep mode control input (internal 200kΩ pull-down); logic high enables device; logic low enters low-power sleep mode (2µA per page 10); pulse clears fault latches per section 7.4.3." }, { "number": "27", "name": "CPL", "type": "power_in",- "description": "Charge pump lower switching node; connect X7R 0.022\u00b5F ceramic capacitor (VM rated) between CPL and CPH per section 7.3.5."+ "description": "Charge pump lower switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPL and CPH per section 7.3.5." }, { "number": "28", "name": "CPH", "type": "power_out",- "description": "Charge pump upper switching node; connect X7R 0.022\u00b5F ceramic capacitor (VM rated) between CPH and CPL for gate driver supply per section 7.3.5."+ "description": "Charge pump upper switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPH and CPL for gate driver supply per section 7.3.5." }, { "number": "29",@@ -302,5 +302,8 @@ "docs/drv8424epwpr-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ]+ ],+ "visibility": {+ "public": true+ } }