component
DRV8424EPWPR
Public Made by Adomby adom
Texas Instruments Stepper Motor Driver, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8424EPWPR
Texas Instruments · Stepper Motor Driver · HTSSOP-28-EP
DRV8424EPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCP | power_out | Charge pump output; connect 0.22µF 16V ceramic capacitor to VM for high-side gate driver power. |
| 2 | VM | power_in | Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9. |
| 3 | PGND | power_in | Power supply ground connection. |
| 4 | AOUT1 | output | Motor winding A output capable of 4A peak current (DRV8424E per page 1). |
| 5 | AOUT1 | output | Motor winding A output capable of 4A peak current; parallel connection to pin 4 for current distribution. |
| 6 | AOUT2 | output | Motor winding A output capable of 4A peak current. |
| 7 | AOUT2 | output | Motor winding A output capable of 4A peak current; parallel connection to pin 6 for current distribution. |
| 8 | BOUT2 | output | Motor winding B output capable of 4A peak current. |
| 9 | BOUT2 | output | Motor winding B output capable of 4A peak current; parallel connection to pin 8 for current distribution. |
| 10 | BOUT1 | output | Motor winding B output capable of 4A peak current. |
| 11 | BOUT1 | output | Motor winding B output capable of 4A peak current; parallel connection to pin 10 for current distribution. |
| 12 | PGND | power_in | Power supply ground connection. |
| 13 | VM | power_in | Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9. |
| 14 | GND | power_in | Logic circuit ground; connect to system ground. |
| 15 | DVDD | power_in | Logic supply voltage (4.75-5.25V typical, section 6.5); bypass with 0.47-1µF X7R ceramic capacitor rated 6.3V or 10V. |
| 16 | nFAULT | tri_state | Fault indicator output (open-drain); pulled to logic low on VM UVLO, VCP UVLO, overcurrent (4A threshold), or overtemperature faults; requires external pull-up resistor. |
| 17 | VREFB | input | Bridge B current reference voltage input (0.05-2.64V per section 6.3); sets full-scale chopping current via IREG = VREFB / 1.32 V/A. |
| 18 | VREFA | input | Bridge A current reference voltage input (0.05-3.3V per section 6.3); sets full-scale chopping current via IREG = VREFA / 1.32 V/A. |
| 19 | TOFF | input | PWM turn-off time selection (four-level pin): 7µs (GND), 16µs (DVDD), 24µs (high impedance), or 32µs (330kΩ to GND) per table 7-4 page 19. |
| 20 | BDECAY | input | Bridge B decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19. |
| 21 | ADECAY | input | Bridge A decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19. |
| 22 | BPH | input | Bridge B phase input (PH/EN interface); logic high drives current from BOUT1 to BOUT2; logic low reverses direction per table 7-2 page 17. |
| 23 | BEN | input | Bridge B enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17. |
| 24 | APH | input | Bridge A phase input (PH/EN interface); logic high drives current from AOUT1 to AOUT2; logic low reverses direction per table 7-2 page 17. |
| 25 | AEN | input | Bridge A enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17. |
| 26 | nSLEEP | input | Sleep mode control input (internal 200kΩ pull-down); logic high enables device; logic low enters low-power sleep mode (2µA per page 10); pulse clears fault latches per section 7.4.3. |
| 27 | CPL | power_in | Charge pump lower switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPL and CPH per section 7.3.5. |
| 28 | CPH | power_out | Charge pump upper switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPH and CPL for gate driver supply per section 7.3.5. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Motor Driver ICs |
| Pins | 29 |
CAD (KiCad official)
- Symbol:
DRV8424EPWPR - Footprint:
Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm - 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files:
drv8424epwpr-etched.step/drv8424epwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8424epwpr.step/drv8424epwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (53 pp, sha256
61208cc09b733204, retrieved 2026-09-26, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).