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DRV8424EPWPR
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Texas Instruments Stepper Motor Driver, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+66@@ -0,0 +1,66 @@+# DRV8424EPWPR++**Texas Instruments** · Stepper Motor Driver · HTSSOP-28-EP++DRV8424EPWPR from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VCP | power_out | Charge pump output; connect 0.22µF 16V ceramic capacitor to VM for high-side gate driver power. |+| 2 | VM | power_in | Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9. |+| 3 | PGND | power_in | Power supply ground connection. |+| 4 | AOUT1 | output | Motor winding A output capable of 4A peak current (DRV8424E per page 1). |+| 5 | AOUT1 | output | Motor winding A output capable of 4A peak current; parallel connection to pin 4 for current distribution. |+| 6 | AOUT2 | output | Motor winding A output capable of 4A peak current. |+| 7 | AOUT2 | output | Motor winding A output capable of 4A peak current; parallel connection to pin 6 for current distribution. |+| 8 | BOUT2 | output | Motor winding B output capable of 4A peak current. |+| 9 | BOUT2 | output | Motor winding B output capable of 4A peak current; parallel connection to pin 8 for current distribution. |+| 10 | BOUT1 | output | Motor winding B output capable of 4A peak current. |+| 11 | BOUT1 | output | Motor winding B output capable of 4A peak current; parallel connection to pin 10 for current distribution. |+| 12 | PGND | power_in | Power supply ground connection. |+| 13 | VM | power_in | Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9. |+| 14 | GND | power_in | Logic circuit ground; connect to system ground. |+| 15 | DVDD | power_in | Logic supply voltage (4.75-5.25V typical, section 6.5); bypass with 0.47-1µF X7R ceramic capacitor rated 6.3V or 10V. |+| 16 | nFAULT | tri_state | Fault indicator output (open-drain); pulled to logic low on VM UVLO, VCP UVLO, overcurrent (4A threshold), or overtemperature faults; requires external pull-up resistor. |+| 17 | VREFB | input | Bridge B current reference voltage input (0.05-2.64V per section 6.3); sets full-scale chopping current via IREG = VREFB / 1.32 V/A. |+| 18 | VREFA | input | Bridge A current reference voltage input (0.05-3.3V per section 6.3); sets full-scale chopping current via IREG = VREFA / 1.32 V/A. |+| 19 | TOFF | input | PWM turn-off time selection (four-level pin): 7µs (GND), 16µs (DVDD), 24µs (high impedance), or 32µs (330kΩ to GND) per table 7-4 page 19. |+| 20 | BDECAY | input | Bridge B decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19. |+| 21 | ADECAY | input | Bridge A decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19. |+| 22 | BPH | input | Bridge B phase input (PH/EN interface); logic high drives current from BOUT1 to BOUT2; logic low reverses direction per table 7-2 page 17. |+| 23 | BEN | input | Bridge B enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17. |+| 24 | APH | input | Bridge A phase input (PH/EN interface); logic high drives current from AOUT1 to AOUT2; logic low reverses direction per table 7-2 page 17. |+| 25 | AEN | input | Bridge A enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17. |+| 26 | nSLEEP | input | Sleep mode control input (internal 200kΩ pull-down); logic high enables device; logic low enters low-power sleep mode (2µA per page 10); pulse clears fault latches per section 7.4.3. |+| 27 | CPL | power_in | Charge pump lower switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPL and CPH per section 7.3.5. |+| 28 | CPH | power_out | Charge pump upper switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPH and CPL for gate driver supply per section 7.3.5. |+| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-28-EP |+| Category | Motor Driver ICs |+| Pins | 29 |++## CAD (KiCad official)++- Symbol: `DRV8424EPWPR`+- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`+- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)+- 3D model files: `drv8424epwpr-etched.step` / `drv8424epwpr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8424epwpr.step` / `drv8424epwpr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8424e) (53 pp, sha256 `61208cc09b733204`, retrieved 2026-09-26, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8424epwpr-datasheet.pdf)
page.jsonadded+285@@ -0,0 +1,285 @@+{+ "slug": "drv8424epwpr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Stepper Motor Driver, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8424epwpr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8424epwpr.kicad_sym",+ "drv8424epwpr.kicad_mod",+ "drv8424epwpr.glb",+ "drv8424epwpr.step",+ "drv8424epwpr.lbr",+ "docs/hero.png",+ "docs/drv8424epwpr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8424EPWPR",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-28-EP",+ "pin_count": 29,+ "category": "Motor Driver ICs",+ "subcategory": "Stepper Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8424e",+ "parts": {+ "symbol": "drv8424epwpr.kicad_sym",+ "footprint": "drv8424epwpr.kicad_mod",+ "model_3d": "drv8424epwpr-etched.glb",+ "model_3d_plain": "drv8424epwpr.glb",+ "model_3d_step": "drv8424epwpr-etched.step",+ "model_3d_step_plain": "drv8424epwpr.step",+ "lbr": "drv8424epwpr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2862906",+ "digikey": "296-DRV8424EPWPRTR-ND",+ "mouser": "595-DRV8424EPWPR"+ },+ "distributor_check": {+ "checked_at": "2026-09-26T22:55:58Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DRV8424EPWPRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DRV8424EPWPR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output; connect 0.22µF 16V ceramic capacitor to VM for high-side gate driver power."+ },+ {+ "number": "2",+ "name": "VM",+ "type": "power_in",+ "description": "Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9."+ },+ {+ "number": "3",+ "name": "PGND",+ "type": "power_in",+ "description": "Power supply ground connection."+ },+ {+ "number": "4",+ "name": "AOUT1",+ "type": "output",+ "description": "Motor winding A output capable of 4A peak current (DRV8424E per page 1)."+ },+ {+ "number": "5",+ "name": "AOUT1",+ "type": "output",+ "description": "Motor winding A output capable of 4A peak current; parallel connection to pin 4 for current distribution."+ },+ {+ "number": "6",+ "name": "AOUT2",+ "type": "output",+ "description": "Motor winding A output capable of 4A peak current."+ },+ {+ "number": "7",+ "name": "AOUT2",+ "type": "output",+ "description": "Motor winding A output capable of 4A peak current; parallel connection to pin 6 for current distribution."+ },+ {+ "number": "8",+ "name": "BOUT2",+ "type": "output",+ "description": "Motor winding B output capable of 4A peak current."+ },+ {+ "number": "9",+ "name": "BOUT2",+ "type": "output",+ "description": "Motor winding B output capable of 4A peak current; parallel connection to pin 8 for current distribution."+ },+ {+ "number": "10",+ "name": "BOUT1",+ "type": "output",+ "description": "Motor winding B output capable of 4A peak current."+ },+ {+ "number": "11",+ "name": "BOUT1",+ "type": "output",+ "description": "Motor winding B output capable of 4A peak current; parallel connection to pin 10 for current distribution."+ },+ {+ "number": "12",+ "name": "PGND",+ "type": "power_in",+ "description": "Power supply ground connection."+ },+ {+ "number": "13",+ "name": "VM",+ "type": "power_in",+ "description": "Motor power supply (4.5-33V); bypass each pin with 0.01µF ceramic capacitor and bulk capacitor to PGND per section 9."+ },+ {+ "number": "14",+ "name": "GND",+ "type": "power_in",+ "description": "Logic circuit ground; connect to system ground."+ },+ {+ "number": "15",+ "name": "DVDD",+ "type": "power_in",+ "description": "Logic supply voltage (4.75-5.25V typical, section 6.5); bypass with 0.47-1µF X7R ceramic capacitor rated 6.3V or 10V."+ },+ {+ "number": "16",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator output (open-drain); pulled to logic low on VM UVLO, VCP UVLO, overcurrent (4A threshold), or overtemperature faults; requires external pull-up resistor."+ },+ {+ "number": "17",+ "name": "VREFB",+ "type": "input",+ "description": "Bridge B current reference voltage input (0.05-2.64V per section 6.3); sets full-scale chopping current via IREG = VREFB / 1.32 V/A."+ },+ {+ "number": "18",+ "name": "VREFA",+ "type": "input",+ "description": "Bridge A current reference voltage input (0.05-3.3V per section 6.3); sets full-scale chopping current via IREG = VREFA / 1.32 V/A."+ },+ {+ "number": "19",+ "name": "TOFF",+ "type": "input",+ "description": "PWM turn-off time selection (four-level pin): 7µs (GND), 16µs (DVDD), 24µs (high impedance), or 32µs (330kΩ to GND) per table 7-4 page 19."+ },+ {+ "number": "20",+ "name": "BDECAY",+ "type": "input",+ "description": "Bridge B decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19."+ },+ {+ "number": "21",+ "name": "ADECAY",+ "type": "input",+ "description": "Bridge A decay mode selection (four-level pin); selects smart-tune dynamic, smart-tune ripple, hybrid, or fast decay modes per table 7-5 page 19."+ },+ {+ "number": "22",+ "name": "BPH",+ "type": "input",+ "description": "Bridge B phase input (PH/EN interface); logic high drives current from BOUT1 to BOUT2; logic low reverses direction per table 7-2 page 17."+ },+ {+ "number": "23",+ "name": "BEN",+ "type": "input",+ "description": "Bridge B enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17."+ },+ {+ "number": "24",+ "name": "APH",+ "type": "input",+ "description": "Bridge A phase input (PH/EN interface); logic high drives current from AOUT1 to AOUT2; logic low reverses direction per table 7-2 page 17."+ },+ {+ "number": "25",+ "name": "AEN",+ "type": "input",+ "description": "Bridge A enable input (PH/EN interface); logic high enables bridge; logic low disables bridge to high impedance per table 7-2 page 17."+ },+ {+ "number": "26",+ "name": "nSLEEP",+ "type": "input",+ "description": "Sleep mode control input (internal 200kΩ pull-down); logic high enables device; logic low enters low-power sleep mode (2µA per page 10); pulse clears fault latches per section 7.4.3."+ },+ {+ "number": "27",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump lower switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPL and CPH per section 7.3.5."+ },+ {+ "number": "28",+ "name": "CPH",+ "type": "power_out",+ "description": "Charge pump upper switching node; connect X7R 0.022µF ceramic capacitor (VM rated) between CPH and CPL for gate driver supply per section 7.3.5."+ },+ {+ "number": "29",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 29 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 53,+ "cost_usd": 0.6327,+ "at": "2026-09-26T22:55:41"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8424e",+ "pages": 53,+ "sha256": "61208cc09b733204",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 29,+ "described": 29,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}