DRV8411ARTER from TI, in a WQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PGNDA	power_in	Device power ground for full bridge A (AOUT1, AOUT2). Connect to system ground.
2	AOUT2	output	Bridge A output 2.
3	BOUT2	output	Bridge B output 2.
4	PGNDB	power_in	Device power ground for full bridge B (BOUT1, BOUT2). Connect to system ground.
5	BOUT1	output	Bridge B output 1.
6	nFAULT	output	Fault indicator output. Pulled low during a fault condition. Connect an external pullup resistor for open-drain operation.
7	BIN1	input	H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 8.4.1. Internal pulldown resistor.
8	BIN2	input	H-bridge control input for full bridge B (BOUT1, BOUT2). See Section 8.4.1. Internal pulldown resistor.
9	BIPROPI	output	Analog current output proportional to load current for full bridge B (BOUT1, BOUT2). See Section 8.4.2.
10	VM	power_in	1.65-V to 11-V power supply input. Connect a 0.1-µF bypass capacitor to ground, as well as sufficient Bulk Capacitance rated for VM.
11	GND	power_in	Device ground. Connect to system ground.
12	AIPROPI	output	Analog current output proportional to load current for full bridge A (AOUT1, AOUT2). See Section 8.4.2.
13	AIN2	input	H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 8.4.1. Internal pulldown resistor.
14	AIN1	input	H-bridge control input for full bridge A (AOUT1, AOUT2). See Section 8.4.1. Internal pulldown resistor.
15	VREF	power_in	External reference voltage input to set internal current regulation limit..See Section 8.4.2.
16	AOUT1	output	Bridge A output 1.
17	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	TI
Package	WQFN-16-EP(3x3)
Category	Power Management ICs
Pins	17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply pin voltage VM	VM	-0.5		12	V		5
Power supply transient voltage ramp VM		0		2	V/µs		5
Voltage difference between ground pins GND, PGNDA, PGNDB		-0.6		0.6	V		5
Logic pin voltage AIN1, AIN2, BIN1, BIN2		-0.3		5.75	V		5
Open-drain output pin voltage nFAULT		0.3		5.75	V		5
Proportional current output pin voltage AIPROPI, BIPROPI		-0.3		5.75	V	VM ≥ 5.45 V	5
Proportional current output pin voltage AIPROPI, BIPROPI		-0.3			V	VM < 5.45 V; max printed as VVM + 0.3 V	5
Reference input pin voltage VREF		0.3		5.75	V		5
Ambient temperature TA	TA	-40		125	°C		5
Junction temperature TJ	TJ	-40		150	°C		5
Storage temperature Tstg	Tstg	-65		150	°C		5
Power supply voltage VM	VVM	1.65		11	V		5
Logic input voltage AIN1, AIN2, BIN1, BIN2	VIN	0		5.5	V		5
PWM frequency AIN1, AIN2, BIN1, BIN2	fPWM	0		100	kHz		5
Open drain pullup voltage nFAULT	VOD	0		5.5	V		5
Open drain output current nFAULT	IOD	0		5	mA		5
Peak output current OUTx	IOUT	0			A	max IOCP,min	5
Current sense output current AIPROPI, BIPROPI	IIPROPI	0		1	mA		5
Current limit reference voltage VREF	VVREF	0		3.6	V	VM ≥ 3.6 V	5
Current limit reference voltage VREF	VVREF	0			V	VM < 3.6 V; max printed as VM	5
Operating ambient temperature TA	TA	-40		125	°C		5
Operating junction temperature TJ	TJ	-40		150	°C		6
Junction-to-ambient thermal resistance RθJA (RTE WQFN)	RθJA		49.7		°C/W		6
Junction-to-case (top) thermal resistance RθJC(top) (RTE WQFN)	RθJC(top)		50.9		°C/W		6
Junction-to-board thermal resistance RθJB (RTE WQFN)	RθJB		23.5		°C/W		6
Junction-to-top characterization parameter ΨJT (RTE WQFN)	ΨJT		1.7		°C/W		6
Junction-to-board characterization parameter ΨJB (RTE WQFN)	ΨJB		23.5		°C/W		6
Junction-to-case (bottom) thermal resistance RθJC(bot) (RTE WQFN)	RθJC(bot)		10.8		°C/W		6
VM sleep mode current	IVMQ		4	40	nA	VVM = 5 V, TJ = 27°C	6
VM active mode current	IVM		2.3	4	mA	xIN1 = 3.3 V, xIN2 = 0 V, VVM = 5 V	6
Autosleep turnoff time	tAUTOSLEEP		0.7	1.5	ms	Active mode to autosleep mode delay	6
Input logic low voltage	VIL	0		0.4	V		6
Input logic high voltage	VIH	1.45		5.5	V		6
Input logic low current	IIL	-1		1	µA	VxINx = 0 V	6
Input logic high current	IIH	20		70	µA	VxINx = 5 V	6
Output logic low voltage	VOL			0.3	V	IOD = 5 mA	6
Output logic high current	IOZ	-1		1	µA	VOD = 5 V	6
Current mirror total error AERR	AERR	-6		6	%	IOUT = 1 A, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 3.3 V ≤ VVM ≤ 11 V	7
Current mirror total error AERR	AERR	-9		6	%	IOUT = 1 A, VIPROPI ≤ min(VM-1.25 V, 3.3 V), 1.65 V ≤ VVM ≤ 3.3 V	7
Thermal shutdown temperature TTSD	TTSD	153		193	°C		7

CAD (KiCad official)

Symbol: DRV8411ARTER
Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
3D model: WQFN-16-EP(3x3) (KiCad packages3D, STEP)
3D model files: drv8411arter-etched.step / drv8411arter-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8411arter.step / drv8411arter.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TI datasheet (50 pp, sha256 9b42a38051293555, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

DRV8411ARTER

Verified DRV8411ARTER

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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