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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

DRV8410PWPR

Texas Instruments · New Arrivals · HTSSOP-16

DRV8410PWPR from Texas Instruments, in a HTSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	nSLEEP	input	Sleep-mode input: logic high enables the device and logic low enters low-power sleep; accepts 0 to 5.5 V with an internal 500 kΩ pulldown.
2	AOUT1	output	Bridge A output 1 of the H-bridge driving AOUT1/AOUT2; output voltage is limited to -VSD to VVM+VSD.
3	AISEN	passive	Bridge A current-sense pin: connect to the bridge A sense resistor, or directly to GND if current regulation is not needed; absolute limits are -0.6 V to 0.6 V.
4	AOUT2	output	Bridge A output 2 of the H-bridge driving AOUT1/AOUT2; output voltage is limited to -VSD to VVM+VSD.
5	BOUT2	output	Bridge B output 2 of the H-bridge driving BOUT1/BOUT2; output voltage is limited to -VSD to VVM+VSD.
6	BISEN	passive	Bridge B current-sense pin: connect to the bridge B sense resistor, or directly to GND if current regulation is not needed; absolute limits are -0.6 V to 0.6 V.
7	BOUT1	output	Bridge B output 1 of the H-bridge driving BOUT1/BOUT2; output voltage is limited to -VSD to VVM+VSD.
8	nFAULT	output	Open-drain fault indication output, pulled low during fault conditions; requires an external pull-up, 0 to 5.5 V, sinking up to 5 mA.
9	BIN1	input	H-bridge B control input for BOUT1/BOUT2; accepts 0 to 5.5 V logic with an internal 100 kΩ pulldown.
10	BIN2	input	H-bridge B control input for BOUT1/BOUT2; accepts 0 to 5.5 V logic with an internal 100 kΩ pulldown.
11	NC	unconnected	No internal connection.
12	VM	power_in	Power supply input, 1.65 V to 11 V (absolute maximum 12 V); bypass with a 0.1 µF capacitor to GND and a bulk capacitor rated for VM.
13	GND	power_in	Device ground; connect to the system ground.
14	NC	unconnected	No internal connection.
15	AIN2	input	H-bridge A control input for AOUT1/AOUT2; accepts 0 to 5.5 V logic with an internal 100 kΩ pulldown.
16	AIN1	input	H-bridge A control input for AOUT1/AOUT2; accepts 0 to 5.5 V logic with an internal 100 kΩ pulldown.
17	PAD	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-16
Category	Others
Pins	17

CAD (KiCad official)

Symbol: DRV8410PWPR
Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
3D model: HTSSOP-16 (KiCad packages3D, STEP)
3D model files: drv8410pwpr-etched.step / drv8410pwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8410pwpr.step / drv8410pwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (49 pp, sha256 e8c8d08f3d01f406, retrieved 2026-10-11, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF