component
DRV8353SRTAT
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
drv8353srtat: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+90−10
package.json+48−8@@ -65,13 +65,13 @@ "number": "3", "name": "VM", "type": "power_in",- "description": "Gate driver power supply input, 9 to 75 V operating voltage range, 0.1-\u00b5F and \u226510-\u00b5F bypass capacitance required."+ "description": "Gate driver power supply input, 9 to 75 V operating voltage range, 0.1-µF and ≥10-µF bypass capacitance required." }, { "number": "4", "name": "VDRAIN", "type": "power_in",- "description": "High-side MOSFET drain sense input and charge pump reference, 7 to 100 V operating range, maximum 2 V/\u00b5s slew rate."+ "description": "High-side MOSFET drain sense input and charge pump reference, 7 to 100 V operating range, maximum 2 V/µs slew rate." }, { "number": "5",@@ -191,7 +191,7 @@ "number": "24", "name": "VREF", "type": "power_in",- "description": "Shunt amplifier reference voltage input, 3 to 5.5 V operating range, 0.1-\u00b5F ceramic bypass capacitor required."+ "description": "Shunt amplifier reference voltage input, 3 to 5.5 V operating range, 0.1-µF ceramic bypass capacitor required." }, { "number": "25",@@ -233,7 +233,7 @@ "number": "31", "name": "ENABLE", "type": "input",- "description": "Gate driver enable input, logic low enters low-power sleep mode, 8 to 40 \u00b5s pulse resets latched faults."+ "description": "Gate driver enable input, logic low enters low-power sleep mode, 8 to 40 µs pulse resets latched faults." }, { "number": "32",@@ -275,7 +275,7 @@ "number": "38", "name": "DVDD", "type": "power_out",- "description": "5-V internal regulator output with up to 10 mA external load capability, 1-\u00b5F 6.3-V bypass capacitor required."+ "description": "5-V internal regulator output with up to 10 mA external load capability, 1-µF 6.3-V bypass capacitor required." }, { "number": "39",@@ -287,7 +287,7 @@ "number": "40", "name": "VGLS", "type": "power_out",- "description": "11-V internal regulator output with 25 mA average capability, 1-\u00b5F 16-V bypass capacitor required."+ "description": "11-V internal regulator output with 25 mA average capability, 1-µF 16-V bypass capacitor required." }, { "number": "41",@@ -331,6 +331,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353srtat.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353srtat-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "7512bdc0948bc907357047dd746bc8fc2b2fc004f29ff2ccbf6c08ab75c58e35",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -316,7 +316,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353srtat.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353srtat-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "7512bdc0948bc907357047dd746bc8fc2b2fc004f29ff2ccbf6c08ab75c58e35",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -363,4 +403,4 @@ "visibility": { "public": true }-}+}