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DRV8353SRTAT

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by adom

Texas Instruments Global Sourcing Parts, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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DRV8353SRTAT

Texas Instruments · Global Sourcing Parts · WQFN-40-EP(6x6)

DRV8353SRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPL power_in Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins.
2 CPH power_in Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins.
3 VM power_in Gate driver power supply input, 9 to 75 V operating voltage range, 0.1-µF and ≥10-µF bypass capacitance required.
4 VDRAIN power_in High-side MOSFET drain sense input and charge pump reference, 7 to 100 V operating range, maximum 2 V/µs slew rate.
5 VCP power_out Charge pump output regulated to VDRAIN + 10.5 V nominal with 25 mA average output current capability.
6 GHA output High-side gate driver output for phase A, up to 1 A peak source current, 9 to 12 V output voltage range.
7 SHA input High-side source sense input for phase A, -5 to 102 V absolute maximum, connect to high-side MOSFET source.
8 GLA output Low-side gate driver output for phase A, up to 2 A peak sink current, 9 to 12 V output voltage range.
9 SPA input Low-side source sense and shunt amplifier input for phase A, -1 to 1 V operating range, connect to low-side MOSFET source.
10 SNA input Shunt amplifier negative input for phase A, -1 to 1 V operating range, connect to low-side of current shunt resistor.
11 SNB input Shunt amplifier negative input for phase B, -1 to 1 V operating range, connect to low-side of current shunt resistor.
12 SPB input Low-side source sense and shunt amplifier input for phase B, -1 to 1 V operating range, connect to low-side MOSFET source.
13 GLB output Low-side gate driver output for phase B, up to 2 A peak sink current, 9 to 12 V output voltage range.
14 SHB input High-side source sense input for phase B, -5 to 102 V absolute maximum, connect to high-side MOSFET source.
15 GHB output High-side gate driver output for phase B, up to 1 A peak source current, 9 to 12 V output voltage range.
16 GHC output High-side gate driver output for phase C, up to 1 A peak source current, 9 to 12 V output voltage range.
17 SHC input High-side source sense input for phase C, -5 to 102 V absolute maximum, connect to high-side MOSFET source.
18 GLC output Low-side gate driver output for phase C, up to 2 A peak sink current, 9 to 12 V output voltage range.
19 SPC input Low-side source sense and shunt amplifier input for phase C, -1 to 1 V operating range, connect to low-side MOSFET source.
20 SNC input Shunt amplifier negative input for phase C, -1 to 1 V operating range, connect to low-side of current shunt resistor.
21 SOC output Shunt amplifier output for phase C, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V.
22 SOB output Shunt amplifier output for phase B, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V.
23 SOA output Shunt amplifier output for phase A, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V.
24 VREF power_in Shunt amplifier reference voltage input, 3 to 5.5 V operating range, 0.1-µF ceramic bypass capacitor required.
25 AGND power_in Device analog ground for shunt amplifier and analog circuitry.
26 nFAULT tri_state Open-drain fault indicator output pulled logic low during fault condition, requires external pullup resistor.
27 SDO tri_state SPI serial data output, open-drain configuration, data shifted on SCLK rising edge, requires external pullup resistor.
28 SDI input SPI serial data input, data captured on SCLK falling edge, minimum 100 ns SCLK period supported.
29 SCLK input SPI serial clock input, 100 ns minimum period, 50 ns minimum high and low times required.
30 nSCS input SPI chip select input, logic low enables serial communication, 400 ns minimum high time between frames.
31 ENABLE input Gate driver enable input, logic low enters low-power sleep mode, 8 to 40 µs pulse resets latched faults.
32 INHA input High-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
33 INLA input Low-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
34 INHB input High-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
35 INLB input Low-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
36 INHC input High-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
37 INLC input Low-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay.
38 DVDD power_out 5-V internal regulator output with up to 10 mA external load capability, 1-µF 6.3-V bypass capacitor required.
39 GND power_in Device power ground for connection to system ground plane.
40 VGLS power_out 11-V internal regulator output with 25 mA average capability, 1-µF 16-V bypass capacitor required.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Global Sourcing Parts
Pins 41

CAD (KiCad official)

  • Symbol: DRV8353SRTAT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: drv8353srtat-etched.step / drv8353srtat-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8353srtat.step / drv8353srtat.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 4ab34376642b461e, retrieved 2026-09-24, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF