component
DRV8353SRTAT
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8353SRTAT++**Texas Instruments** · Global Sourcing Parts · WQFN-40-EP(6x6)++DRV8353SRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPL | power_in | Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins. |+| 2 | CPH | power_in | Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins. |+| 3 | VM | power_in | Gate driver power supply input, 9 to 75 V operating voltage range, 0.1-µF and ≥10-µF bypass capacitance required. |+| 4 | VDRAIN | power_in | High-side MOSFET drain sense input and charge pump reference, 7 to 100 V operating range, maximum 2 V/µs slew rate. |+| 5 | VCP | power_out | Charge pump output regulated to VDRAIN + 10.5 V nominal with 25 mA average output current capability. |+| 6 | GHA | output | High-side gate driver output for phase A, up to 1 A peak source current, 9 to 12 V output voltage range. |+| 7 | SHA | input | High-side source sense input for phase A, -5 to 102 V absolute maximum, connect to high-side MOSFET source. |+| 8 | GLA | output | Low-side gate driver output for phase A, up to 2 A peak sink current, 9 to 12 V output voltage range. |+| 9 | SPA | input | Low-side source sense and shunt amplifier input for phase A, -1 to 1 V operating range, connect to low-side MOSFET source. |+| 10 | SNA | input | Shunt amplifier negative input for phase A, -1 to 1 V operating range, connect to low-side of current shunt resistor. |+| 11 | SNB | input | Shunt amplifier negative input for phase B, -1 to 1 V operating range, connect to low-side of current shunt resistor. |+| 12 | SPB | input | Low-side source sense and shunt amplifier input for phase B, -1 to 1 V operating range, connect to low-side MOSFET source. |+| 13 | GLB | output | Low-side gate driver output for phase B, up to 2 A peak sink current, 9 to 12 V output voltage range. |+| 14 | SHB | input | High-side source sense input for phase B, -5 to 102 V absolute maximum, connect to high-side MOSFET source. |+| 15 | GHB | output | High-side gate driver output for phase B, up to 1 A peak source current, 9 to 12 V output voltage range. |+| 16 | GHC | output | High-side gate driver output for phase C, up to 1 A peak source current, 9 to 12 V output voltage range. |+| 17 | SHC | input | High-side source sense input for phase C, -5 to 102 V absolute maximum, connect to high-side MOSFET source. |+| 18 | GLC | output | Low-side gate driver output for phase C, up to 2 A peak sink current, 9 to 12 V output voltage range. |+| 19 | SPC | input | Low-side source sense and shunt amplifier input for phase C, -1 to 1 V operating range, connect to low-side MOSFET source. |+| 20 | SNC | input | Shunt amplifier negative input for phase C, -1 to 1 V operating range, connect to low-side of current shunt resistor. |+| 21 | SOC | output | Shunt amplifier output for phase C, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V. |+| 22 | SOB | output | Shunt amplifier output for phase B, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V. |+| 23 | SOA | output | Shunt amplifier output for phase A, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V. |+| 24 | VREF | power_in | Shunt amplifier reference voltage input, 3 to 5.5 V operating range, 0.1-µF ceramic bypass capacitor required. |+| 25 | AGND | power_in | Device analog ground for shunt amplifier and analog circuitry. |+| 26 | nFAULT | tri_state | Open-drain fault indicator output pulled logic low during fault condition, requires external pullup resistor. |+| 27 | SDO | tri_state | SPI serial data output, open-drain configuration, data shifted on SCLK rising edge, requires external pullup resistor. |+| 28 | SDI | input | SPI serial data input, data captured on SCLK falling edge, minimum 100 ns SCLK period supported. |+| 29 | SCLK | input | SPI serial clock input, 100 ns minimum period, 50 ns minimum high and low times required. |+| 30 | nSCS | input | SPI chip select input, logic low enables serial communication, 400 ns minimum high time between frames. |+| 31 | ENABLE | input | Gate driver enable input, logic low enters low-power sleep mode, 8 to 40 µs pulse resets latched faults. |+| 32 | INHA | input | High-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 33 | INLA | input | Low-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 34 | INHB | input | High-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 35 | INLB | input | Low-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 36 | INHC | input | High-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 37 | INLC | input | Low-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay. |+| 38 | DVDD | power_out | 5-V internal regulator output with up to 10 mA external load capability, 1-µF 6.3-V bypass capacitor required. |+| 39 | GND | power_in | Device power ground for connection to system ground plane. |+| 40 | VGLS | power_out | 11-V internal regulator output with 25 mA average capability, 1-µF 16-V bypass capacitor required. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-40-EP(6x6) |+| Category | Global Sourcing Parts |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8353SRTAT`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8353srtat-etched.step` / `drv8353srtat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8353srtat.step` / `drv8353srtat.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8353) (101 pp, sha256 `4ab34376642b461e`, retrieved 2026-09-24, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8353srtat-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "global sourcing parts",+ "drv8353srtat",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8353srtat.kicad_sym",+ "drv8353srtat.kicad_mod",+ "drv8353srtat.glb",+ "drv8353srtat.step",+ "drv8353srtat.lbr",+ "docs/hero.png",+ "docs/drv8353srtat-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8353SRTAT",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Global Sourcing Parts",+ "subcategory": "Global Sourcing Parts",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8353",+ "parts": {+ "symbol": "drv8353srtat.kicad_sym",+ "footprint": "drv8353srtat.kicad_mod",+ "model_3d": "drv8353srtat-etched.glb",+ "model_3d_plain": "drv8353srtat.glb",+ "model_3d_step": "drv8353srtat-etched.step",+ "model_3d_step_plain": "drv8353srtat.step",+ "lbr": "drv8353srtat.lbr"+ },+ "distributor_links": {+ "lcsc": "C2150480"+ },+ "pins": [+ {+ "number": "1",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump switching node requiring X5R or X7R 47-nF VDRAIN-rated capacitor connection between CPH and CPL pins."+ },+ {+ "number": "3",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input, 9 to 75 V operating voltage range, 0.1-µF and ≥10-µF bypass capacitance required."+ },+ {+ "number": "4",+ "name": "VDRAIN",+ "type": "power_in",+ "description": "High-side MOSFET drain sense input and charge pump reference, 7 to 100 V operating range, maximum 2 V/µs slew rate."+ },+ {+ "number": "5",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output regulated to VDRAIN + 10.5 V nominal with 25 mA average output current capability."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output for phase A, up to 1 A peak source current, 9 to 12 V output voltage range."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "input",+ "description": "High-side source sense input for phase A, -5 to 102 V absolute maximum, connect to high-side MOSFET source."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output for phase A, up to 2 A peak sink current, 9 to 12 V output voltage range."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input for phase A, -1 to 1 V operating range, connect to low-side MOSFET source."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Shunt amplifier negative input for phase A, -1 to 1 V operating range, connect to low-side of current shunt resistor."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Shunt amplifier negative input for phase B, -1 to 1 V operating range, connect to low-side of current shunt resistor."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input for phase B, -1 to 1 V operating range, connect to low-side MOSFET source."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output for phase B, up to 2 A peak sink current, 9 to 12 V output voltage range."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "input",+ "description": "High-side source sense input for phase B, -5 to 102 V absolute maximum, connect to high-side MOSFET source."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output for phase B, up to 1 A peak source current, 9 to 12 V output voltage range."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output for phase C, up to 1 A peak source current, 9 to 12 V output voltage range."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "input",+ "description": "High-side source sense input for phase C, -5 to 102 V absolute maximum, connect to high-side MOSFET source."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output for phase C, up to 2 A peak sink current, 9 to 12 V output voltage range."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input for phase C, -1 to 1 V operating range, connect to low-side MOSFET source."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Shunt amplifier negative input for phase C, -1 to 1 V operating range, connect to low-side of current shunt resistor."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Shunt amplifier output for phase C, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Shunt amplifier output for phase B, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Shunt amplifier output for phase A, 0.25 to VREF - 0.25 V linear output range, programmable gain of 5, 10, 20, or 40 V/V."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Shunt amplifier reference voltage input, 3 to 5.5 V operating range, 0.1-µF ceramic bypass capacitor required."+ },+ {+ "number": "25",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground for shunt amplifier and analog circuitry."+ },+ {+ "number": "26",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Open-drain fault indicator output pulled logic low during fault condition, requires external pullup resistor."+ },+ {+ "number": "27",+ "name": "SDO",+ "type": "tri_state",+ "description": "SPI serial data output, open-drain configuration, data shifted on SCLK rising edge, requires external pullup resistor."+ },+ {+ "number": "28",+ "name": "SDI",+ "type": "input",+ "description": "SPI serial data input, data captured on SCLK falling edge, minimum 100 ns SCLK period supported."+ },+ {+ "number": "29",+ "name": "SCLK",+ "type": "input",+ "description": "SPI serial clock input, 100 ns minimum period, 50 ns minimum high and low times required."+ },+ {+ "number": "30",+ "name": "nSCS",+ "type": "input",+ "description": "SPI chip select input, logic low enables serial communication, 400 ns minimum high time between frames."+ },+ {+ "number": "31",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input, logic low enters low-power sleep mode, 8 to 40 µs pulse resets latched faults."+ },+ {+ "number": "32",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "33",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input for phase A, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "34",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "35",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input for phase B, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "36",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "37",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input for phase C, 0 to 5.5 V logic levels, 200 ns typical propagation delay."+ },+ {+ "number": "38",+ "name": "DVDD",+ "type": "power_out",+ "description": "5-V internal regulator output with up to 10 mA external load capability, 1-µF 6.3-V bypass capacitor required."+ },+ {+ "number": "39",+ "name": "GND",+ "type": "power_in",+ "description": "Device power ground for connection to system ground plane."+ },+ {+ "number": "40",+ "name": "VGLS",+ "type": "power_out",+ "description": "11-V internal regulator output with 25 mA average capability, 1-µF 16-V bypass capacitor required."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: DRV8353SRTAT is the SPI variant with integrated 3-phase shunt amplifiers but no integrated buck regu",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 101,+ "cost_usd": 1.1831,+ "at": "2026-09-24T05:24:27"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8353",+ "pages": 101,+ "sha256": "4ab34376642b461e",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}