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DRV8353SRTAR

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Texas Instruments Global Sourcing Parts, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentglobal sourcing partsdrv8353srtarfactory-2.0.0extractor-text

Verified DRV8353SRTAR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: DRV8353SRTAR · WQFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 101-page datasheet
  • ✓distributor: lcsc C701785, digikey 296-DRV8353SRTARTR-ND, mouser 595-DRV8353SRTAR
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qrtnhlet/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ drv8353srtar.kicad_sym✓ drv8353srtar.kicad_mod✓ drv8353srtar.step
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Ray Publish 0.1.0 b21118f 6h ago

DRV8353SRTAR

Texas Instruments · Global Sourcing Parts · WQFN-40-EP(6x6)

DRV8353SRTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPL passive Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL.
2 CPH passive Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL.
3 VM power_in Gate driver power supply input; connect to VDRAIN or a separate gate driver supply, with a X5R or X7R 0.1-µF VM-rated capacitor and at least 10 µF local capacitance to GND.
4 VDRAIN input High-side MOSFET drain sense input and charge pump reference; connect to the common point of the MOSFET drains.
5 VCP power_out Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VCP and VDRAIN.
6 GHA output High-side gate driver output; connect to the gate of the high-side power MOSFET.
7 SHA input High-side source sense input; connect to the high-side power MOSFET source.
8 GLA output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
9 SPA input Low-side source sense and shunt amplifier input; connect to the low-side MOSFET source and high side of the current shunt resistor.
10 SNA input Shunt amplifier input; connect to the low side of the current shunt resistor.
11 SNB input Shunt amplifier input; connect to the low side of the current shunt resistor.
12 SPB input Low-side source sense and shunt amplifier input; connect to the low-side MOSFET source and high side of the current shunt resistor.
13 GLB output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
14 SHB input High-side source sense input; connect to the high-side power MOSFET source.
15 GHB output High-side gate driver output; connect to the gate of the high-side power MOSFET.
16 GHC output High-side gate driver output; connect to the gate of the high-side power MOSFET.
17 SHC input High-side source sense input; connect to the high-side power MOSFET source.
18 GLC output Low-side gate driver output; connect to the gate of the low-side power MOSFET.
19 SPC input Low-side source sense and shunt amplifier input; connect to the low-side MOSFET source and high side of the current shunt resistor.
20 SNC input Shunt amplifier input; connect to the low side of the current shunt resistor.
21 SOC output Shunt amplifier output.
22 SOB output Shunt amplifier output.
23 SOA output Shunt amplifier output.
24 VREF power_in Shunt amplifier power supply input and reference; connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between VREF and AGND.
25 AGND power_in Device analog ground; connect to system ground.
26 nFAULT output Open-drain fault indicator output; pulled logic low during a fault condition and requires an external pullup resistor.
27 SDO output Open-drain serial data output; data is shifted out on the rising edge of SCLK and requires an external pullup resistor.
28 SDI input Serial data input; data is captured on the falling edge of SCLK.
29 SCLK input Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges of this pin.
30 nSCS input Serial chip select; a logic low on this pin enables serial interface communication.
31 ENABLE input Gate driver enable; a logic low puts the device into low power sleep mode, and an 8 to 40-µs low pulse can be used to reset fault conditions.
32 INHA input High-side gate driver control input; this pin controls the output of the high-side gate driver.
33 INLA input Low-side gate driver control input; this pin controls the output of the low-side gate driver.
34 INHB input High-side gate driver control input; this pin controls the output of the high-side gate driver.
35 INLB input Low-side gate driver control input; this pin controls the output of the low-side gate driver.
36 INHC input High-side gate driver control input; this pin controls the output of the high-side gate driver.
37 INLC input Low-side gate driver control input; this pin controls the output of the low-side gate driver.
38 DVDD power_out 5-V internal regulator output; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between DVDD and GND, and it can source up to 10 mA externally.
39 GND power_in Device power ground; connect to system ground.
40 VGLS power_out 11-V internal regulator output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-40-EP(6x6)
Category Global Sourcing Parts
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply pin voltage VM -0.3 80 V 10
MOSFET drain sense pin voltage VDRAIN -0.3 102 V 10
Low-side gate drive regulator pin voltage VGLS -0.3 18 V 10
Internal logic regulator pin voltage DVDD -0.3 5.75 V 10
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) -0.3 5.75 V 10
Continuous shunt amplifier input pin voltage (SNx, SPx) -1 1 V 10
Ambient temperature TA -40 125 °C 10
Junction temperature TJ -40 150 °C 10
Gate driver power supply voltage (VM) VVM 9 75 V 11
Charge pump reference and drain voltage sense (VDRAIN) VVDRAIN 7 100 V 11
Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) VI 0 5.5 V 11
Applied PWM signal (INHx, INLx) fPWM 0 200 kHz 11
High-side average gate-drive current (GHx) IGATE_HS 0 25 mA 11
Low-side average gate-drive current (GLx) IGATE_LS 0 25 mA 11
External load current (DVDD) IDVDD 0 10 mA 11
Reference voltage input (VREF) VVREF 3 5.5 V 11
Operating ambient temperature TA -40 125 °C 11
Operating junction temperature TJ -40 150 °C 11
VM operating supply current IVM 8.5 13 mA VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 12
VDRAIN operating supply current IVDRAIN 1.9 4 mA VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 12
Sleep mode supply current ISLEEP 20 40 µA ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C 12
Sleep mode supply current ISLEEP 100 µA ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C 12
Reset pulse time tRST 5 40 µs ENABLE = 0 V period to reset faults 12
DVDD regulator voltage VDVDD 4.75 5 5.25 V IDVDD = 0 to 10 mA 12
VCP operating voltage with respect to VDRAIN VVCP 9 10.5 12 V VVM = 15 V, IVCP = 0 to 25 mA 12
VCP operating voltage with respect to VDRAIN VVCP 5.5 7.5 8.5 V VVM = 9 V, IVCP = 0 to 10 mA 12
VGLS operating voltage with respect to GND VVGLS 13 14.5 16 V VVM = 15 V, IVGLS = 0 to 25 mA 12
VGLS operating voltage with respect to GND VVGLS 7 8.5 9.5 V VVM = 9 V, IVGLS = 0 to 10 mA 12
Input logic low voltage VIL 0 0.8 V 12
Input logic high voltage VIH 1.5 5.5 V 12
Input logic high current IIH 50 70 µA VVIN = 5 V 12
Output logic low voltage VOL 0.125 V IO = 5 mA 12
Output high impedance leakage IOZ -2 2 µA VO = 5 V 12
High-side gate drive voltage with respect to SHx VGSH 9 10.5 12 V VVM = 15 V, IVCP = 0 to 25 mA 13
High-side gate drive voltage with respect to SHx VGSH 5.5 7.5 8.5 V VVM = 9 V, IVCP = 0 to 10 mA 13
Low-side gate drive voltage with respect to PGND VGSL 9.5 11 12.5 V VVM = 15 V, IVGLS = 0 to 25 mA 13
Low-side gate drive voltage with respect to PGND VGSL 6.5 8 9.5 V VVM = 9 V, IVGLS = 0 to 10 mA 13
Amplifier gain GCSA 4.85 5 5.15 V/V CSA_GAIN = 00b 14
Amplifier gain GCSA 9.7 10 10.3 V/V CSA_GAIN = 01b 14
Amplifier gain GCSA 19.4 20 20.6 V/V CSA_GAIN = 10b 14
Amplifier gain GCSA 38.8 40 41.2 V/V CSA_GAIN = 11b 14
Common mode input range VCOM -0.15 0.15 V 14
Differential mode input range VDIFF -0.3 0.3 V 14
Input offset error VOFF -3 3 mV VSP = VSN = 0 V 14
SOx output voltage linear range VLINEAR 0.25 V 14
VM undervoltage lockout VVM_UV 8 8.3 8.8 V DRV835x: VM falling, UVLO report 15
VM undervoltage lockout VVM_UV 8.2 8.5 9 V DRV835x: VM rising, UVLO recovery 15
VDRAIN undervoltage lockout VVDR_UV 6.1 6.4 6.8 V DRV835x: VDRAIN falling, UVLO report 15
VDRAIN undervoltage lockout VVDR_UV 6.3 6.6 7 V DRV835x: VDRAIN rising, UVLO recovery 15
High-side gate clamp positive clamping voltage VGS_CLAMP 12.5 13.5 16 V Positive clamping voltage 15
Thermal warning temperature TOTW 130 150 170 °C Die temperature, TJ 16
Thermal shutdown temperature TOTSD 150 170 190 °C Die temperature, TJ 16
VDS overcurrent trip voltage VVDS_OCP 0.041 0.06 0.072 V DRV835x: VDS_LVL = 0000b 16
VDS overcurrent trip voltage VVDS_OCP 1.8 2 2.2 V VDS_LVL = 1111b 16
SCLK minimum period tCLK 100 ns 18
SDO output data delay time tD_SDO 30 ns SCLK high to SDO valid 18
Junction-to-ambient thermal resistance RθJA 26.1 °C/W RTA (WQFN), 40 pins 11
Junction-to-case (top) thermal resistance RθJC(top) 13.1 °C/W RTA (WQFN), 40 pins 11
Junction-to-board thermal resistance RθJB 8.4 °C/W RTA (WQFN), 40 pins 11
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.1 °C/W RTA (WQFN), 40 pins 11

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper into the feedback pin. • Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input 78

CAD (KiCad official)

  • Symbol: DRV8353SRTAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: drv8353srtar-etched.step / drv8353srtar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8353srtar.step / drv8353srtar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 8bb3a1d29ec9ea07, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF