component
DRV8353RSRGZT
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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8353RSRGZT
Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-48-EP(7x7)
DRV8353RSRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device power ground. Connect to system ground. |
| 2 | VGLS | power_out | 11-V internal regulator output. Connect a 1-µF, 16-V ceramic capacitor between VGLS and GND pins. |
| 3 | CPL | passive | Charge pump switching node. Connect a 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL pins. |
| 4 | CPH | passive | Charge pump switching node. Connect a 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL pins. |
| 5 | VM | power_in | Gate driver power supply input. Connect to VDRAIN or separate supply voltage with 0.1-µF and 10-µF capacitors to GND. |
| 6 | VDRAIN | input | High-side MOSFET drain sense input and charge pump reference. Connect to common point of MOSFET drains. |
| 7 | VCP | power_out | Charge pump output. Connect a 1-µF, 16-V ceramic capacitor between VCP and VDRAIN pins. |
| 8 | GHA | output | High-side gate driver output for phase A. Connect to gate of high-side power MOSFET. |
| 9 | SHA | input | High-side source sense input for phase A. Connect to high-side power MOSFET source. |
| 10 | GLA | output | Low-side gate driver output for phase A. Connect to gate of low-side power MOSFET. |
| 11 | SPA | input | Low-side source sense and shunt amplifier input for phase A. Connect to MOSFET source and shunt resistor high side. |
| 12 | SNA | input | Shunt amplifier input for phase A. Connect to low-side of current shunt resistor. |
| 13 | SNB | input | Shunt amplifier input for phase B. Connect to low-side of current shunt resistor. |
| 14 | SPB | input | Low-side source sense and shunt amplifier input for phase B. Connect to MOSFET source and shunt resistor high side. |
| 15 | GLB | output | Low-side gate driver output for phase B. Connect to gate of low-side power MOSFET. |
| 16 | SHB | input | High-side source sense input for phase B. Connect to high-side power MOSFET source. |
| 17 | GHB | output | High-side gate driver output for phase B. Connect to gate of high-side power MOSFET. |
| 18 | GHC | output | High-side gate driver output for phase C. Connect to gate of high-side power MOSFET. |
| 19 | SHC | input | High-side source sense input for phase C. Connect to high-side power MOSFET source. |
| 20 | GLC | output | Low-side gate driver output for phase C. Connect to gate of low-side power MOSFET. |
| 21 | SPC | input | Low-side source sense and shunt amplifier input for phase C. Connect to MOSFET source and shunt resistor high side. |
| 22 | SNC | input | Shunt amplifier input for phase C. Connect to low-side of current shunt resistor. |
| 23 | SOC | output | Shunt amplifier output for phase C. |
| 24 | SOB | output | Shunt amplifier output for phase B. |
| 25 | SOA | output | Shunt amplifier output for phase A. |
| 26 | VREF | power_in | Shunt amplifier power supply input and reference. Connect a 0.1-µF, 6.3-V capacitor between VREF and AGND pins. |
| 27 | AGND | power_in | Device analog ground. Connect to system ground. |
| 28 | nFAULT | tri_state | Fault indicator output, open-drain. Pin is pulled low during fault condition and requires external pullup resistor. |
| 29 | SDO | tri_state | Serial data output, open-drain. Data is shifted out on rising edge of SCLK and requires external pullup resistor. |
| 30 | SDI | input | Serial data input. Data is captured on falling edge of SCLK pin. |
| 31 | SCLK | input | Serial clock input. Serial data is shifted and captured on corresponding edges of this clock pin. |
| 32 | nSCS | input | Serial chip select. Logic low on this pin enables serial interface communication. |
| 33 | ENABLE | input | Gate driver enable. Logic low puts device in sleep mode; 8 to 40-µs pulse resets fault conditions. |
| 34 | INHA | input | High-side gate driver control input for phase A. Controls output of high-side gate driver. |
| 35 | INLA | input | Low-side gate driver control input for phase A. Controls output of low-side gate driver. |
| 36 | INHB | input | High-side gate driver control input for phase B. Controls output of high-side gate driver. |
| 37 | INLB | input | Low-side gate driver control input for phase B. Controls output of low-side gate driver. |
| 38 | INHC | input | High-side gate driver control input for phase C. Controls output of high-side gate driver. |
| 39 | INLC | input | Low-side gate driver control input for phase C. Controls output of low-side gate driver. |
| 40 | DVDD | power_out | 5-V internal regulator output. Connect a 1-µF, 6.3-V capacitor between DVDD and DGND pins; can source 10 mA. |
| 41 | DGND | power_in | Device digital ground. Connect to system ground. |
| 42 | SW | output | Buck switch node. Connect to inductor, diode, and bootstrap capacitor. |
| 43 | VIN | power_in | Buck regulator power supply input, 6 V to 100 V. Place VM-rated ceramic capacitor between VIN and GND. |
| 44 | VCC | power_out | 7-V internal regulator output for buck switch gate supply. Connect 0.47-µF, 16-V capacitor between VCC and GND. |
| 45 | BST | passive | Buck regulator bootstrap input. Connect 0.01-µF, 16-V capacitor between BST and SW pins. |
| 46 | RCL | input | Current limit off-time set input. Connect resistor between RCL and GND to set buck current limit timing. |
| 47 | RT/SD | input | Buck on-time set and remote shutdown input. Connect resistor between RT/SD and VIN to set buck switching frequency. |
| 48 | FB | input | Buck feedback input. Resistor divider from post-inductor output to this pin sets buck output voltage. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Motor Driver ICs |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DRV8353RSRGZT - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
drv8353rsrgzt-etched.step/drv8353rsrgzt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8353rsrgzt.step/drv8353rsrgzt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (101 pp, sha256
4ab34376642b461e, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).