component
DRV8353RHRGZR
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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8353RHRGZR
Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-48-EP(7x7)
DRV8353RHRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device power ground. Connect to system ground. |
| 2 | VGLS | power_out | 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins. |
| 3 | CPL | power_out | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. |
| 4 | CPH | power_out | Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL pins. |
| 5 | VM | power_in | Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage with 0.1-µF, VM-rated ceramic and ≥10-µF local capacitance between the VM and GND pins. |
| 6 | VDRAIN | power_in | High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains. |
| 7 | VCP | power_out | Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins. |
| 8 | GHA | output | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| 9 | SHA | input | High-side source sense input. Connect to the high-side power MOSFET source. |
| 10 | GLA | output | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| 11 | SPA | input | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| 12 | SNA | input | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| 13 | SNB | input | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| 14 | SPB | input | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| 15 | GLB | output | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| 16 | SHB | input | High-side source sense input. Connect to the high-side power MOSFET source. |
| 17 | GHB | output | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| 18 | GHC | output | High-side gate driver output. Connect to the gate of the high-side power MOSFET. |
| 19 | SHC | input | High-side source sense input. Connect to the high-side power MOSFET source. |
| 20 | GLC | output | Low-side gate driver output. Connect to the gate of the low-side power MOSFET. |
| 21 | SPC | input | Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current shunt resistor. |
| 22 | SNC | input | Shunt amplifier input. Connect to the low-side of the current shunt resistor. |
| 23 | SOC | output | Shunt amplifier output. |
| 24 | SOB | output | Shunt amplifier output. |
| 25 | SOA | output | Shunt amplifier output. |
| 26 | VREF | power_out | Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins. |
| 27 | AGND | power_in | Device analog ground. Connect to system ground. |
| 28 | nFAULT | tri_state | Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor. |
| 29 | MODE | input | PWM input mode setting. This pin is a 4 level input pin set by an external resistor. |
| 30 | IDRIVE | input | Gate drive output current setting. This pin is a 7 level input pin set by an external resistor. |
| 31 | VDS | input | VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor. |
| 32 | GAIN | input | Amplifier gain setting. The pin is a 4 level input pin set by an external resistor. |
| 33 | ENABLE | input | Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be used to reset fault conditions. |
| 34 | INHA | input | High-side gate driver control input. This pin controls the output of the high-side gate driver. |
| 35 | INLA | input | Low-side gate driver control input. This pin controls the output of the low-side gate driver. |
| 36 | INHB | input | High-side gate driver control input. This pin controls the output of the high-side gate driver. |
| 37 | INLB | input | Low-side gate driver control input. This pin controls the output of the low-side gate driver. |
| 38 | INHC | input | High-side gate driver control input. This pin controls the output of the high-side gate driver. |
| 39 | INLC | input | Low-side gate driver control input. This pin controls the output of the low-side gate driver. |
| 40 | DVDD | power_out | 5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and DGND pins. This regulator can source up to 10 mA externally. |
| 41 | DGND | power_in | Device digital ground. Connect to system ground. |
| 42 | SW | output | Buck switch node. Connect this pin to an inductor, diode, and the CB bootstrap capacitor. |
| 43 | VIN | power_in | Buck regulator power supply input. Place an X5R or X7R, VM-rated ceramic capacitor between the VIN and GND pins. |
| 44 | VCC | power_out | 7-V internal regulator output. Gate supply for buck switch. Connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between the VCC and GND pins. |
| 45 | BST | power_in | Buck regulator bootstrap input. Connect a X5R or X7R, 0.01-µF, 16-V, capacitor between the BST and SW pins. |
| 46 | RCL | input | Current limit off time set input. Connect a resistor between RCL and GND. |
| 47 | RT/SD | input | On time set and remote shutdown input. Connect a resistor between RT/SD and VIN. |
| 48 | FB | input | Buck feedback input. A resistor divider from the buck post inductor output to this pin sets the buck output voltage. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Motor Driver ICs |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DRV8353RHRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
drv8353rhrgzr-etched.step/drv8353rhrgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8353rhrgzr.step/drv8353rhrgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (101 pp, sha256
4ab34376642b461e, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).