component
DRV8353FSRTAR
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
drv8353fsrtar: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
2 files changed
+90−10
package.json+48−8@@ -65,7 +65,7 @@ "number": "3", "name": "VM", "type": "power_in",- "description": "Gate driver power supply input (9-75V recommended); connect 0.1\u00b5F bypass and \u226510\u00b5F bulk capacitor."+ "description": "Gate driver power supply input (9-75V recommended); connect 0.1µF bypass and ≥10µF bulk capacitor." }, { "number": "4",@@ -77,7 +77,7 @@ "number": "5", "name": "VCP", "type": "power_out",- "description": "Charge pump output (\u2248VDRAIN+10.5V); connect 1\u00b5F, 16V filter capacitor to VDRAIN."+ "description": "Charge pump output (≈VDRAIN+10.5V); connect 1µF, 16V filter capacitor to VDRAIN." }, { "number": "6",@@ -191,7 +191,7 @@ "number": "24", "name": "VREF", "type": "power_in",- "description": "Shunt amplifier reference voltage input (3-5.5V recommended); connect 0.1\u00b5F, 6.3V capacitor to AGND."+ "description": "Shunt amplifier reference voltage input (3-5.5V recommended); connect 0.1µF, 6.3V capacitor to AGND." }, { "number": "25",@@ -233,7 +233,7 @@ "number": "31", "name": "ENABLE", "type": "input",- "description": "Gate driver enable input; logic low activates low-power sleep mode, 8-40\u00b5s pulse resets faults."+ "description": "Gate driver enable input; logic low activates low-power sleep mode, 8-40µs pulse resets faults." }, { "number": "32",@@ -275,7 +275,7 @@ "number": "38", "name": "DVDD", "type": "power_out",- "description": "5V internal regulator output (\u00b15% regulated); connect 1\u00b5F, 6.3V capacitor to GND (10mA max load)."+ "description": "5V internal regulator output (±5% regulated); connect 1µF, 6.3V capacitor to GND (10mA max load)." }, { "number": "39",@@ -287,7 +287,7 @@ "number": "40", "name": "VGLS", "type": "power_out",- "description": "11V internal regulator output; connect 1\u00b5F, 16V capacitor to GND (25mA max, further regulated to 11V at GLx outputs)."+ "description": "11V internal regulator output; connect 1µF, 16V capacitor to GND (25mA max, further regulated to 11V at GLx outputs)." }, { "number": "41",@@ -330,6 +330,46 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353fsrtar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353fsrtar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "6e4e0012ea35afde3987df73f022354959ec0ab5e60cd04b3ab47cbd83e71f71",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }-}+}
page.json+42−2@@ -315,7 +315,47 @@ "viewers": { "symbol": "viewers/symbol.html", "footprint": "viewers/footprint.html"- }+ },+ "models_3d": [+ {+ "file": "drv8353fsrtar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8353fsrtar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.0,+ 6.0,+ 1.0+ ],+ "zmin_mm": 0.0,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "6e4e0012ea35afde3987df73f022354959ec0ab5e60cd04b3ab47cbd83e71f71",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ] }, "metadata": { "specs": {@@ -363,4 +403,4 @@ "public": true }, "updated_at": "2026-09-24T20:00:05.529Z"-}+}