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DRV8353FSRTAR
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Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8353FSRTAR++**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)++DRV8353FSRTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPL | output | Charge pump switch node; connect 47nF external capacitor between CPH and CPL. |+| 2 | CPH | output | Charge pump switch node; connect 47nF external capacitor between CPH and CPL. |+| 3 | VM | power_in | Gate driver power supply input (9-75V recommended); connect 0.1µF bypass and ≥10µF bulk capacitor. |+| 4 | VDRAIN | input | High side MOSFET drain sense input and charge pump reference (7-100V recommended). |+| 5 | VCP | power_out | Charge pump output (≈VDRAIN+10.5V); connect 1µF, 16V filter capacitor to VDRAIN. |+| 6 | GHA | output | High side gate driver output for phase A; connect to high side MOSFET gate. |+| 7 | SHA | input | High side source sense input for phase A; connect to high side MOSFET source. |+| 8 | GLA | output | Low side gate driver output for phase A; connect to low side MOSFET gate. |+| 9 | SPA | input | Low side source sense and shunt amplifier positive input for phase A; connect to MOSFET source and sense resistor high side. |+| 10 | SNA | input | Shunt amplifier negative sense input for phase A; connect to current sense resistor low side. |+| 11 | SNB | input | Shunt amplifier negative sense input for phase B; connect to current sense resistor low side. |+| 12 | SPB | input | Low side source sense and shunt amplifier positive input for phase B; connect to MOSFET source and sense resistor high side. |+| 13 | GLB | output | Low side gate driver output for phase B; connect to low side MOSFET gate. |+| 14 | SHB | input | High side source sense input for phase B; connect to high side MOSFET source. |+| 15 | GHB | output | High side gate driver output for phase B; connect to high side MOSFET gate. |+| 16 | GHC | output | High side gate driver output for phase C; connect to high side MOSFET gate. |+| 17 | SHC | input | High side source sense input for phase C; connect to high side MOSFET source. |+| 18 | GLC | output | Low side gate driver output for phase C; connect to low side MOSFET gate. |+| 19 | SPC | input | Low side source sense and shunt amplifier positive input for phase C; connect to MOSFET source and sense resistor high side. |+| 20 | SNC | input | Shunt amplifier negative sense input for phase C; connect to current sense resistor low side. |+| 21 | SOC | output | Shunt amplifier output for phase C; provides amplified current sense signal. |+| 22 | SOB | output | Shunt amplifier output for phase B; provides amplified current sense signal. |+| 23 | SOA | output | Shunt amplifier output for phase A; provides amplified current sense signal. |+| 24 | VREF | power_in | Shunt amplifier reference voltage input (3-5.5V recommended); connect 0.1µF, 6.3V capacitor to AGND. |+| 25 | AGND | power_in | Device analog ground; connect to system ground for circuit reference. |+| 26 | nFAULT | tri_state | Fault indicator output (open-drain, active low); requires external pull-up resistor to VCC. |+| 27 | SDO | tri_state | Serial data output (open-drain); data shifts out on SCLK rising edge, requires pull-up resistor. |+| 28 | SDI | input | Serial data input; data captured on SCLK falling edge for SPI communication. |+| 29 | SCLK | input | Serial clock input; synchronizes SPI data capture and output timing. |+| 30 | nSCS | input | Serial chip select (active low); logic low enables SPI interface communication. |+| 31 | ENABLE | input | Gate driver enable input; logic low activates low-power sleep mode, 8-40µs pulse resets faults. |+| 32 | INHA | input | High side gate driver control input for phase A; directly controls high side gate output. |+| 33 | INLA | input | Low side gate driver control input for phase A; directly controls low side gate output. |+| 34 | INHB | input | High side gate driver control input for phase B; directly controls high side gate output. |+| 35 | INLB | input | Low side gate driver control input for phase B; directly controls low side gate output. |+| 36 | INHC | input | High side gate driver control input for phase C; directly controls high side gate output. |+| 37 | INLC | input | Low side gate driver control input for phase C; directly controls low side gate output. |+| 38 | DVDD | power_out | 5V internal regulator output (±5% regulated); connect 1µF, 6.3V capacitor to GND (10mA max load). |+| 39 | GND | power_in | Device power ground; connect to system ground for proper circuit operation. |+| 40 | VGLS | power_out | 11V internal regulator output; connect 1µF, 16V capacitor to GND (25mA max, further regulated to 11V at GLx outputs). |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-40-EP(6x6) |+| Category | Motor Driver ICs |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8353FSRTAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8353fsrtar-etched.step` / `drv8353fsrtar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8353fsrtar.step` / `drv8353fsrtar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8353f) (83 pp, sha256 `e84c59e0a37d8b2f`, retrieved 2026-09-22, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8353fsrtar-datasheet.pdf)
page.jsonadded+341@@ -0,0 +1,341 @@+{+ "slug": "drv8353fsrtar",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8353fsrtar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8353fsrtar.kicad_sym",+ "drv8353fsrtar.kicad_mod",+ "drv8353fsrtar.glb",+ "drv8353fsrtar.step",+ "drv8353fsrtar.lbr",+ "docs/hero.png",+ "docs/drv8353fsrtar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8353FSRTAR",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Motor Driver ICs",+ "subcategory": "Brushless DC (BLDC) Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8353f",+ "parts": {+ "symbol": "drv8353fsrtar.kicad_sym",+ "footprint": "drv8353fsrtar.kicad_mod",+ "model_3d": "drv8353fsrtar-etched.glb",+ "model_3d_plain": "drv8353fsrtar.glb",+ "model_3d_step": "drv8353fsrtar-etched.step",+ "model_3d_step_plain": "drv8353fsrtar.step",+ "lbr": "drv8353fsrtar.lbr"+ },+ "distributor_links": {+ "lcsc": "C1518717"+ },+ "pins": [+ {+ "number": "1",+ "name": "CPL",+ "type": "output",+ "description": "Charge pump switch node; connect 47nF external capacitor between CPH and CPL."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "output",+ "description": "Charge pump switch node; connect 47nF external capacitor between CPH and CPL."+ },+ {+ "number": "3",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input (9-75V recommended); connect 0.1µF bypass and ≥10µF bulk capacitor."+ },+ {+ "number": "4",+ "name": "VDRAIN",+ "type": "input",+ "description": "High side MOSFET drain sense input and charge pump reference (7-100V recommended)."+ },+ {+ "number": "5",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output (≈VDRAIN+10.5V); connect 1µF, 16V filter capacitor to VDRAIN."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High side gate driver output for phase A; connect to high side MOSFET gate."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "input",+ "description": "High side source sense input for phase A; connect to high side MOSFET source."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low side gate driver output for phase A; connect to low side MOSFET gate."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low side source sense and shunt amplifier positive input for phase A; connect to MOSFET source and sense resistor high side."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Shunt amplifier negative sense input for phase A; connect to current sense resistor low side."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Shunt amplifier negative sense input for phase B; connect to current sense resistor low side."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low side source sense and shunt amplifier positive input for phase B; connect to MOSFET source and sense resistor high side."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low side gate driver output for phase B; connect to low side MOSFET gate."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "input",+ "description": "High side source sense input for phase B; connect to high side MOSFET source."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High side gate driver output for phase B; connect to high side MOSFET gate."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High side gate driver output for phase C; connect to high side MOSFET gate."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "input",+ "description": "High side source sense input for phase C; connect to high side MOSFET source."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low side gate driver output for phase C; connect to low side MOSFET gate."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low side source sense and shunt amplifier positive input for phase C; connect to MOSFET source and sense resistor high side."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Shunt amplifier negative sense input for phase C; connect to current sense resistor low side."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Shunt amplifier output for phase C; provides amplified current sense signal."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Shunt amplifier output for phase B; provides amplified current sense signal."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Shunt amplifier output for phase A; provides amplified current sense signal."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Shunt amplifier reference voltage input (3-5.5V recommended); connect 0.1µF, 6.3V capacitor to AGND."+ },+ {+ "number": "25",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground; connect to system ground for circuit reference."+ },+ {+ "number": "26",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator output (open-drain, active low); requires external pull-up resistor to VCC."+ },+ {+ "number": "27",+ "name": "SDO",+ "type": "tri_state",+ "description": "Serial data output (open-drain); data shifts out on SCLK rising edge, requires pull-up resistor."+ },+ {+ "number": "28",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input; data captured on SCLK falling edge for SPI communication."+ },+ {+ "number": "29",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; synchronizes SPI data capture and output timing."+ },+ {+ "number": "30",+ "name": "nSCS",+ "type": "input",+ "description": "Serial chip select (active low); logic low enables SPI interface communication."+ },+ {+ "number": "31",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input; logic low activates low-power sleep mode, 8-40µs pulse resets faults."+ },+ {+ "number": "32",+ "name": "INHA",+ "type": "input",+ "description": "High side gate driver control input for phase A; directly controls high side gate output."+ },+ {+ "number": "33",+ "name": "INLA",+ "type": "input",+ "description": "Low side gate driver control input for phase A; directly controls low side gate output."+ },+ {+ "number": "34",+ "name": "INHB",+ "type": "input",+ "description": "High side gate driver control input for phase B; directly controls high side gate output."+ },+ {+ "number": "35",+ "name": "INLB",+ "type": "input",+ "description": "Low side gate driver control input for phase B; directly controls low side gate output."+ },+ {+ "number": "36",+ "name": "INHC",+ "type": "input",+ "description": "High side gate driver control input for phase C; directly controls high side gate output."+ },+ {+ "number": "37",+ "name": "INLC",+ "type": "input",+ "description": "Low side gate driver control input for phase C; directly controls low side gate output."+ },+ {+ "number": "38",+ "name": "DVDD",+ "type": "power_out",+ "description": "5V internal regulator output (±5% regulated); connect 1µF, 6.3V capacitor to GND (10mA max load)."+ },+ {+ "number": "39",+ "name": "GND",+ "type": "power_in",+ "description": "Device power ground; connect to system ground for proper circuit operation."+ },+ {+ "number": "40",+ "name": "VGLS",+ "type": "power_out",+ "description": "11V internal regulator output; connect 1µF, 16V capacitor to GND (25mA max, further regulated to 11V at GLx outputs)."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 83,+ "cost_usd": 0.998,+ "at": "2026-09-22T00:45:03"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8353f",+ "pages": 83,+ "sha256": "e84c59e0a37d8b2f",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}