component
DRV8353FHRTAR
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8353FHRTAR
Texas Instruments · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)
DRV8353FHRTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPL | passive | Charge pump switch node. Connect X5R or X7R 47nF rated voltage VDRAIN ceramic capacitor between CPH and CPL. |
| 2 | CPH | passive | Charge pump switch node. Connect X5R or X7R 47nF rated voltage VDRAIN ceramic capacitor between CPH and CPL. |
| 3 | VM | power_in | Gate driver power supply input rated 9V to 75V. Connect to VDRAIN or separate gate driver power supply with X5R X7R 0.1µF capacitor and local bulk capacitance ≥10µF. |
| 4 | VDRAIN | input | High-side MOSFET drain sensing input and charge pump reference rated 7V to 100V. Connect to common point of MOSFET drain. |
| 5 | VCP | power_out | Charge pump output providing voltage referenced to VDRAIN. Connect X5R or X7R 1µF 16V ceramic capacitor between VCP and VDRAIN. |
| 6 | GHA | output | High-side gate driver output for phase A. Connect to high-side power MOSFET gate with peak current 50mA to 1A. |
| 7 | SHA | input | High-side source sensing input for phase A. Connect to high-side power MOSFET source for gate voltage monitoring. |
| 8 | GLA | output | Low-side gate driver output for phase A. Connect to low-side power MOSFET gate with peak current 100mA to 2A. |
| 9 | SPA | input | Low-side source sensing and shunt amplifier input for phase A. Connect to low-side MOSFET source and shunt resistor high side. |
| 10 | SNA | input | Shunt amplifier input for phase A. Connect to low side of current shunt resistor with common mode range -0.15V to +0.15V. |
| 11 | SNB | input | Shunt amplifier input for phase B. Connect to low side of current shunt resistor with common mode range -0.15V to +0.15V. |
| 12 | SPB | input | Low-side source sensing and shunt amplifier input for phase B. Connect to low-side MOSFET source and shunt resistor high side. |
| 13 | GLB | output | Low-side gate driver output for phase B. Connect to low-side power MOSFET gate with peak current 100mA to 2A. |
| 14 | SHB | input | High-side source sensing input for phase B. Connect to high-side power MOSFET source for gate voltage monitoring. |
| 15 | GHB | output | High-side gate driver output for phase B. Connect to high-side power MOSFET gate with peak current 50mA to 1A. |
| 16 | GHC | output | High-side gate driver output for phase C. Connect to high-side power MOSFET gate with peak current 50mA to 1A. |
| 17 | SHC | input | High-side source sensing input for phase C. Connect to high-side power MOSFET source for gate voltage monitoring. |
| 18 | GLC | output | Low-side gate driver output for phase C. Connect to low-side power MOSFET gate with peak current 100mA to 2A. |
| 19 | SPC | input | Low-side source sensing and shunt amplifier input for phase C. Connect to low-side MOSFET source and shunt resistor high side. |
| 20 | SNC | input | Shunt amplifier input for phase C. Connect to low side of current shunt resistor with common mode range -0.15V to +0.15V. |
| 21 | SOC | output | Shunt amplifier output for phase C providing current sense voltage with gain 5V/V to 40V/V. |
| 22 | SOB | output | Shunt amplifier output for phase B providing current sense voltage with gain 5V/V to 40V/V. |
| 23 | SOA | output | Shunt amplifier output for phase A providing current sense voltage with gain 5V/V to 40V/V. |
| 24 | VREF | power_out | Shunt amplifier power supply and reference voltage 3V to 5.5V. Connect X5R or X7R 0.1µF 6.3V ceramic capacitor between VREF and AGND. |
| 25 | AGND | power_in | Analog ground for shunt amplifier circuits. Connect to system ground. |
| 26 | nFAULT | tri_state | Open-drain fault indicator output pulled to logic low during fault condition. Requires external pull-up resistor to 5.5V. |
| 27 | MODE | input | PWM input mode setting 4-level input via external resistor for hardware interface. Selects 6x 3x 1x or independent PWM mode. |
| 28 | IDRIVE | input | Gate driver output current setting 7-level input via external resistor for hardware interface. Range 50mA pull to 1A pull, 100mA sink to 2A sink. |
| 29 | VDS | input | VDS monitor threshold point setting 7-level input via external resistor for hardware interface. Range 0.06V to 1V for OCP detection. |
| 30 | GAIN | input | Amplifier gain setting 4-level input via external resistor for hardware interface. Selects 5V/V 10V/V 20V/V or 40V/V shunt amplifier gain. |
| 31 | ENABLE | input | Gate driver enable input rated 0V to 5.5V logic levels. Logic low enters sleep mode. 8-40µs low pulse resets latched faults. |
| 32 | INHA | input | High-side gate driver control input for phase A rated 0V to 5.5V logic levels. Controls high-side gate driver output state. |
| 33 | INLA | input | Low-side gate driver control input for phase A rated 0V to 5.5V logic levels. Controls low-side gate driver output state. |
| 34 | INHB | input | High-side gate driver control input for phase B rated 0V to 5.5V logic levels. Controls high-side gate driver output state. |
| 35 | INLB | input | Low-side gate driver control input for phase B rated 0V to 5.5V logic levels. Controls low-side gate driver output state. |
| 36 | INHC | input | High-side gate driver control input for phase C rated 0V to 5.5V logic levels. Controls high-side gate driver output state. |
| 37 | INLC | input | Low-side gate driver control input for phase C rated 0V to 5.5V logic levels. Controls low-side gate driver output state. |
| 38 | DVDD | power_out | 5V internal digital regulator output. Connect X5R or X7R 1µF 6.3V ceramic capacitor between DVDD and GND. Supplies up to 10mA externally. |
| 39 | GND | power_in | Primary power ground and reference for gate drive circuits. Connect to system ground. |
| 40 | VGLS | power_out | 11V internal low-side regulator output. Connect X5R or X7R 1µF 16V ceramic capacitor between VGLS and GND. Supplies low-side gate drive. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Motor Driver ICs |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
DRV8353FHRTAR - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
drv8353fhrtar-etched.step/drv8353fhrtar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8353fhrtar.step/drv8353fhrtar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (83 pp, sha256
e84c59e0a37d8b2f, retrieved 2026-09-18, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).