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DRV8350SRTVT
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Texas Instruments Motor Driver ICs, WQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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DRV8350SRTVT
Texas Instruments · Motor Driver ICs · WQFN-32-EP(5x5)
DRV8350SRTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPH | power_out | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 2 | VM | power_in | Gate driver power supply input; connect to VDRAIN or a separate gate driver supply, with a X5R or X7R 0.1-µF VM-rated capacitor and at least 10 µF of local capacitance to GND. |
| 3 | VDRAIN | input | High-side MOSFET drain sense input and charge pump reference; connect to the common point of the MOSFET drains. |
| 4 | VCP | power_out | Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VCP and VDRAIN. |
| 5 | GHA | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 6 | SHA | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 7 | GLA | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 8 | SLA | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 9 | SLB | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 10 | GLB | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 11 | SHB | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 12 | GHB | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 13 | GHC | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 14 | SHC | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 15 | GLC | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 16 | SLC | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 17 | nFAULT | output | Open-drain fault indicator output; pulled logic low during a fault condition and requires an external pullup resistor. |
| 18 | SDO | output | Open-drain serial data output; data is shifted out on the rising edge of SCLK and the pin requires an external pullup resistor. |
| 19 | SDI | input | Serial data input; data is captured on the falling edge of SCLK. |
| 20 | SCLK | input | Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges of this pin. |
| 21 | nSCS | input | Serial chip select; a logic low on this pin enables serial interface communication. |
| 22 | ENABLE | input | Gate driver enable; a logic low puts the device into low-power sleep mode, and an 8 to 40-µs pulse can be used to reset fault conditions. |
| 23 | INHA | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 24 | INLA | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 25 | INHB | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 26 | INLB | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 27 | INHC | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 28 | INLC | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 29 | DVDD | power_out | 5-V internal regulator output; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between DVDD and GND, and the regulator can source up to 10 mA externally. |
| 30 | GND | power_in | Device primary ground; connect to system ground. |
| 31 | VGLS | power_out | 11-V internal regulator output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND. |
| 32 | CPL | power_out | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage (VM) | -0.3 | 80 | V | 10 | |||
| MOSFET drain sense pin voltage (VDRAIN) | -0.3 | 102 | V | 10 | |||
| Low-side gate drive regulator pin voltage (VGLS) | -0.3 | 18 | V | 10 | |||
| Internal logic regulator pin voltage (DVDD) | -0.3 | 5.75 | V | 10 | |||
| Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) | -0.3 | 5.75 | V | 10 | |||
| Reference input pin voltage (VREF) | -0.3 | 5.75 | V | 10 | |||
| Continuous low-side source sense pin voltage (SLx) | -1 | 1 | V | 10 | |||
| Continuous shunt amplifier input pin voltage (SNx, SPx) | -1 | 1 | V | 10 | |||
| Junction temperature, TJ | TJ | -40 | 150 | °C | 10 | ||
| Ambient temperature, TA | TA | -40 | 125 | °C | 10 | ||
| Gate driver power supply voltage (VM) | VVM | 9 | 75 | V | 11 | ||
| Charge pump reference and drain voltage sense (VDRAIN) | VVDRAIN | 7 | 100 | V | 11 | ||
| Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) | VI | 0 | 5.5 | V | 11 | ||
| Applied PWM signal (INHx, INLx) | fPWM | 0 | 200 | kHz | 11 | ||
| High-side average gate-drive current (GHx) | IGATE_HS | 0 | 25 | mA | 11 | ||
| Low-side average gate-drive current (GLx) | IGATE_LS | 0 | 25 | mA | 11 | ||
| External load current (DVDD) | IDVDD | 0 | 10 | mA | 11 | ||
| Reference voltage input (VREF) | VVREF | 3 | 5.5 | V | 11 | ||
| Shunt amplifier output current (SOx) | ISO | 0 | 5 | mA | 11 | ||
| Open drain pullup voltage (nFAULT, SDO) | VOD | 0 | 5.5 | V | 11 | ||
| Open drain output current (nFAULT, SDO) | IOD | 0 | 5 | mA | 11 | ||
| Operating ambient temperature | TA | -40 | 125 | °C | 11 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 11 | ||
| Junction-to-ambient thermal resistance (32-pin RTV WQFN) | RθJA | 29.2 | °C/W | 11 | |||
| Junction-to-case (top) thermal resistance (32-pin RTV WQFN) | RθJC(top) | 15.2 | °C/W | 11 | |||
| VM operating supply current | IVM | 8.5 | 13 | mA | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 12 | |
| VDRAIN operating supply current | IVDRAIN | 1.9 | 4 | mA | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 12 | |
| Sleep mode supply current | ISLEEP | 20 | 40 | µA | ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C | 12 | |
| Sleep mode supply current | ISLEEP | 100 | µA | ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C | 12 | ||
| Reset pulse time | tRST | 5 | 40 | µs | ENABLE = 0 V period to reset faults | 12 | |
| Turnon time | tWAKE | 1 | ms | VVM > VUVLO, ENABLE = 3.3 V to outputs ready | 12 | ||
| Turnoff time | tSLEEP | 1 | ms | ENABLE = 0 V to device sleep mode | 12 | ||
| DVDD regulator voltage | VDVDD | 4.75 | 5 | 5.25 | V | IDVDD = 0 to 10 mA | 12 |
| VCP operating voltage with respect to VDRAIN | VVCP | 9 | 10.5 | 12 | V | VVM = 15 V, IVCP = 0 to 25 mA | 12 |
| VCP operating voltage with respect to VDRAIN | VVCP | 5.5 | 7.5 | 8.5 | V | VVM = 9 V, IVCP = 0 to 10 mA | 12 |
| VGLS operating voltage with respect to GND | VVGLS | 13 | 14.5 | 16 | V | VVM = 15 V, IVGLS = 0 to 25 mA | 12 |
| VGLS operating voltage with respect to GND | VVGLS | 7 | 8.5 | 9.5 | V | VVM = 9 V, IVGLS = 0 to 10 mA | 12 |
| Input logic low voltage | VIL | 0 | 0.8 | V | 12 | ||
| Input logic high voltage | VIH | 1.5 | 5.5 | V | 12 | ||
| Input logic low current | IIL | -5 | 5 | µA | VVIN = 0 V | 12 | |
| Input logic high current | IIH | 50 | 70 | µA | VVIN = 5 V | 12 | |
| Output logic low voltage | VOL | 0.125 | V | IO = 5 mA | 12 | ||
| Output high impedance leakage | IOZ | -2 | 2 | µA | VO = 5 V | 12 | |
| High-side gate drive voltage with respect to SHx | VGSH | 9 | 10.5 | 12 | V | VVM = 15 V, IVCP = 0 to 25 mA | 13 |
| High-side gate drive voltage with respect to SHx | VGSH | 5.5 | 7.5 | 8.5 | V | VVM = 9 V, IVCP = 0 to 10 mA | 13 |
| Low-side gate drive voltage with respect to PGND | VGSL | 9.5 | 11 | 12.5 | V | VVM = 15 V, IVGLS = 0 to 25 mA | 13 |
| Low-side gate drive voltage with respect to PGND | VGSL | 6.5 | 8 | 9.5 | V | VVM = 9 V, IVGLS = 0 to 10 mA | 13 |
| Amplifier gain | GCSA | 4.85 | 5 | 5.15 | V/V | SPI Device, CSA_GAIN = 00b | 14 |
| Amplifier gain | GCSA | 38.8 | 40 | 41.2 | V/V | SPI Device, CSA_GAIN = 11b | 14 |
| Common mode input range | VCOM | -0.15 | 0.15 | V | 14 | ||
| Differential mode input range | VDIFF | -0.3 | 0.3 | V | 14 | ||
| Input offset error | VOFF | -3 | 3 | mV | VSP = VSN = 0 V | 14 | |
| Drift offset | VDRIFT | 10 | µV/°C | VSP = VSN = 0 V | 14 | ||
| VREF input current | IVREF | 1.5 | 2.5 | mA | VVREF = 5 V | 15 | |
| VM undervoltage lockout (VM falling, UVLO report) | VVM_UV | 8 | 8.3 | 8.8 | V | DRV835x: VM falling, UVLO report | 15 |
| VM undervoltage lockout (VM rising, UVLO recovery) | VVM_UV | 8.2 | 8.5 | 9 | V | DRV835x: VM rising, UVLO recovery | 15 |
| VDRAIN undervoltage lockout (VDRAIN falling, UVLO report) | VVDR_UV | 6.1 | 6.4 | 6.8 | V | DRV835x: VDRAIN falling, UVLO report | 15 |
| VDRAIN undervoltage lockout (VDRAIN rising, UVLO recovery) | VVDR_UV | 6.3 | 6.6 | 7 | V | DRV835x: VDRAIN rising, UVLO recovery | 15 |
| VDS overcurrent trip voltage | VVDS_OCP | 0.041 | 0.06 | 0.072 | V | SPI Device, DRV835x: VDS_LVL = 0000b | 16 |
| VDS overcurrent trip voltage | VVDS_OCP | 1.8 | 2 | 2.2 | V | SPI Device, VDS_LVL = 1111b | 16 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | into the feedback pin. • Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input | 78 |
CAD (KiCad official)
- Symbol:
DRV8350SRTVT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
drv8350srtvt-etched.step/drv8350srtvt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8350srtvt.step/drv8350srtvt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (101 pp, sha256
8bb3a1d29ec9ea07, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# DRV8350SRTVT
**Texas Instruments** · Motor Driver ICs · WQFN-32-EP(5x5)
DRV8350SRTVT from Texas Instruments, in a WQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPH | power_out | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 2 | VM | power_in | Gate driver power supply input; connect to VDRAIN or a separate gate driver supply, with a X5R or X7R 0.1-µF VM-rated capacitor and at least 10 µF of local capacitance to GND. |
| 3 | VDRAIN | input | High-side MOSFET drain sense input and charge pump reference; connect to the common point of the MOSFET drains. |
| 4 | VCP | power_out | Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VCP and VDRAIN. |
| 5 | GHA | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 6 | SHA | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 7 | GLA | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 8 | SLA | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 9 | SLB | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 10 | GLB | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 11 | SHB | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 12 | GHB | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 13 | GHC | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 14 | SHC | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 15 | GLC | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 16 | SLC | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 17 | nFAULT | output | Open-drain fault indicator output; pulled logic low during a fault condition and requires an external pullup resistor. |
| 18 | SDO | output | Open-drain serial data output; data is shifted out on the rising edge of SCLK and the pin requires an external pullup resistor. |
| 19 | SDI | input | Serial data input; data is captured on the falling edge of SCLK. |
| 20 | SCLK | input | Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges of this pin. |
| 21 | nSCS | input | Serial chip select; a logic low on this pin enables serial interface communication. |
| 22 | ENABLE | input | Gate driver enable; a logic low puts the device into low-power sleep mode, and an 8 to 40-µs pulse can be used to reset fault conditions. |
| 23 | INHA | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 24 | INLA | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 25 | INHB | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 26 | INLB | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 27 | INHC | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 28 | INLC | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 29 | DVDD | power_out | 5-V internal regulator output; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between DVDD and GND, and the regulator can source up to 10 mA externally. |
| 30 | GND | power_in | Device primary ground; connect to system ground. |
| 31 | VGLS | power_out | 11-V internal regulator output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND. |
| 32 | CPL | power_out | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-32-EP(5x5) |
| Category | Power Supply Chip |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage (VM) | | -0.3 | | 80 | V | | 10 |
| MOSFET drain sense pin voltage (VDRAIN) | | -0.3 | | 102 | V | | 10 |
| Low-side gate drive regulator pin voltage (VGLS) | | -0.3 | | 18 | V | | 10 |
| Internal logic regulator pin voltage (DVDD) | | -0.3 | | 5.75 | V | | 10 |
| Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO, VDS) | | -0.3 | | 5.75 | V | | 10 |
| Reference input pin voltage (VREF) | | -0.3 | | 5.75 | V | | 10 |
| Continuous low-side source sense pin voltage (SLx) | | -1 | | 1 | V | | 10 |
| Continuous shunt amplifier input pin voltage (SNx, SPx) | | -1 | | 1 | V | | 10 |
| Junction temperature, TJ | TJ | -40 | | 150 | °C | | 10 |
| Ambient temperature, TA | TA | -40 | | 125 | °C | | 10 |
| Gate driver power supply voltage (VM) | VVM | 9 | | 75 | V | | 11 |
| Charge pump reference and drain voltage sense (VDRAIN) | VVDRAIN | 7 | | 100 | V | | 11 |
| Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) | VI | 0 | | 5.5 | V | | 11 |
| Applied PWM signal (INHx, INLx) | fPWM | 0 | | 200 | kHz | | 11 |
| High-side average gate-drive current (GHx) | IGATE_HS | 0 | | 25 | mA | | 11 |
| Low-side average gate-drive current (GLx) | IGATE_LS | 0 | | 25 | mA | | 11 |
| External load current (DVDD) | IDVDD | 0 | | 10 | mA | | 11 |
| Reference voltage input (VREF) | VVREF | 3 | | 5.5 | V | | 11 |
| Shunt amplifier output current (SOx) | ISO | 0 | | 5 | mA | | 11 |
| Open drain pullup voltage (nFAULT, SDO) | VOD | 0 | | 5.5 | V | | 11 |
| Open drain output current (nFAULT, SDO) | IOD | 0 | | 5 | mA | | 11 |
| Operating ambient temperature | TA | -40 | | 125 | °C | | 11 |
| Operating junction temperature | TJ | -40 | | 150 | °C | | 11 |
| Junction-to-ambient thermal resistance (32-pin RTV WQFN) | RθJA | | | 29.2 | °C/W | | 11 |
| Junction-to-case (top) thermal resistance (32-pin RTV WQFN) | RθJC(top) | | | 15.2 | °C/W | | 11 |
| VM operating supply current | IVM | | 8.5 | 13 | mA | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 12 |
| VDRAIN operating supply current | IVDRAIN | | 1.9 | 4 | mA | VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V | 12 |
| Sleep mode supply current | ISLEEP | | 20 | 40 | µA | ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C | 12 |
| Sleep mode supply current | ISLEEP | | | 100 | µA | ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C | 12 |
| Reset pulse time | tRST | 5 | | 40 | µs | ENABLE = 0 V period to reset faults | 12 |
| Turnon time | tWAKE | | | 1 | ms | VVM > VUVLO, ENABLE = 3.3 V to outputs ready | 12 |
| Turnoff time | tSLEEP | | | 1 | ms | ENABLE = 0 V to device sleep mode | 12 |
| DVDD regulator voltage | VDVDD | 4.75 | 5 | 5.25 | V | IDVDD = 0 to 10 mA | 12 |
| VCP operating voltage with respect to VDRAIN | VVCP | 9 | 10.5 | 12 | V | VVM = 15 V, IVCP = 0 to 25 mA | 12 |
| VCP operating voltage with respect to VDRAIN | VVCP | 5.5 | 7.5 | 8.5 | V | VVM = 9 V, IVCP = 0 to 10 mA | 12 |
| VGLS operating voltage with respect to GND | VVGLS | 13 | 14.5 | 16 | V | VVM = 15 V, IVGLS = 0 to 25 mA | 12 |
| VGLS operating voltage with respect to GND | VVGLS | 7 | 8.5 | 9.5 | V | VVM = 9 V, IVGLS = 0 to 10 mA | 12 |
| Input logic low voltage | VIL | 0 | | 0.8 | V | | 12 |
| Input logic high voltage | VIH | 1.5 | | 5.5 | V | | 12 |
| Input logic low current | IIL | -5 | | 5 | µA | VVIN = 0 V | 12 |
| Input logic high current | IIH | | 50 | 70 | µA | VVIN = 5 V | 12 |
| Output logic low voltage | VOL | | | 0.125 | V | IO = 5 mA | 12 |
| Output high impedance leakage | IOZ | -2 | | 2 | µA | VO = 5 V | 12 |
| High-side gate drive voltage with respect to SHx | VGSH | 9 | 10.5 | 12 | V | VVM = 15 V, IVCP = 0 to 25 mA | 13 |
| High-side gate drive voltage with respect to SHx | VGSH | 5.5 | 7.5 | 8.5 | V | VVM = 9 V, IVCP = 0 to 10 mA | 13 |
| Low-side gate drive voltage with respect to PGND | VGSL | 9.5 | 11 | 12.5 | V | VVM = 15 V, IVGLS = 0 to 25 mA | 13 |
| Low-side gate drive voltage with respect to PGND | VGSL | 6.5 | 8 | 9.5 | V | VVM = 9 V, IVGLS = 0 to 10 mA | 13 |
| Amplifier gain | GCSA | 4.85 | 5 | 5.15 | V/V | SPI Device, CSA_GAIN = 00b | 14 |
| Amplifier gain | GCSA | 38.8 | 40 | 41.2 | V/V | SPI Device, CSA_GAIN = 11b | 14 |
| Common mode input range | VCOM | -0.15 | | 0.15 | V | | 14 |
| Differential mode input range | VDIFF | -0.3 | | 0.3 | V | | 14 |
| Input offset error | VOFF | -3 | | 3 | mV | VSP = VSN = 0 V | 14 |
| Drift offset | VDRIFT | | | 10 | µV/°C | VSP = VSN = 0 V | 14 |
| VREF input current | IVREF | 1.5 | | 2.5 | mA | VVREF = 5 V | 15 |
| VM undervoltage lockout (VM falling, UVLO report) | VVM_UV | 8 | 8.3 | 8.8 | V | DRV835x: VM falling, UVLO report | 15 |
| VM undervoltage lockout (VM rising, UVLO recovery) | VVM_UV | 8.2 | 8.5 | 9 | V | DRV835x: VM rising, UVLO recovery | 15 |
| VDRAIN undervoltage lockout (VDRAIN falling, UVLO report) | VVDR_UV | 6.1 | 6.4 | 6.8 | V | DRV835x: VDRAIN falling, UVLO report | 15 |
| VDRAIN undervoltage lockout (VDRAIN rising, UVLO recovery) | VVDR_UV | 6.3 | 6.6 | 7 | V | DRV835x: VDRAIN rising, UVLO recovery | 15 |
| VDS overcurrent trip voltage | VVDS_OCP | 0.041 | 0.06 | 0.072 | V | SPI Device, DRV835x: VDS_LVL = 0000b | 16 |
| VDS overcurrent trip voltage | VVDS_OCP | 1.8 | 2 | 2.2 | V | SPI Device, VDS_LVL = 1111b | 16 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | | into the feedback pin. • Put the input bypass capacitor near the VIN pin to decrease copper trace resistance which effects input | 78 |
## CAD (KiCad official)
- Symbol: `DRV8350SRTVT`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: WQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `drv8350srtvt-etched.step` / `drv8350srtvt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8350srtvt.step` / `drv8350srtvt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8350.pdf) (101 pp, sha256 `8bb3a1d29ec9ea07`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/drv8350srtvt-datasheet.pdf)