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DRV8350RSRGZR
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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8350RSRGZR
Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-48-EP(7x7)
DRV8350RSRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Device primary ground that must be connected to system ground. |
| 2 | VGLS | power_out | 11-V internal regulator output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND. |
| 3 | CPL | passive | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 4 | CPH | passive | Charge pump switching node; connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between CPH and CPL. |
| 5 | VM | power_in | Gate driver power supply input that connects to VDRAIN or a separate gate driver supply, with a X5R or X7R 0.1-µF VM-rated capacitor and at least 10 µF of local capacitance to GND. |
| 6 | VDRAIN | input | High-side MOSFET drain sense input and charge pump reference; connect to the common point of the MOSFET drains. |
| 7 | VCP | power_out | Charge pump output; connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between VCP and VDRAIN. |
| 8 | GHA | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 9 | SHA | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 10 | GLA | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 11 | SLA | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 12 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 13 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 14 | SLB | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 15 | GLB | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 16 | SHB | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 17 | GHB | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 18 | GHC | output | High-side gate driver output; connect to the gate of the high-side power MOSFET. |
| 19 | SHC | input | High-side source sense input; connect to the high-side power MOSFET source. |
| 20 | GLC | output | Low-side gate driver output; connect to the gate of the low-side power MOSFET. |
| 21 | SLC | input | Low-side source sense input; connect to the low-side power MOSFET source. |
| 22 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 23 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 24 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 25 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 26 | NC | unconnected | No internal connection; this pin can be left floating or connected to system ground. |
| 27 | AGND | power_in | Device analog ground that must be connected to system ground. |
| 28 | nFAULT | output | Open-drain fault indicator output that is pulled logic low during a fault and requires an external pullup resistor. |
| 29 | SDO | output | Open-drain serial data output that shifts data out on the rising edge of SCLK and requires an external pullup resistor. |
| 30 | SDI | input | Serial data input; data is captured on the falling edge of SCLK. |
| 31 | SCLK | input | Serial clock input; serial data is shifted out and captured on the corresponding rising and falling edges of this pin. |
| 32 | nSCS | input | Serial chip select; a logic low on this pin enables serial interface communication. |
| 33 | ENABLE | input | Gate driver enable; a logic low puts the device into low-power sleep mode, and an 8 to 40-µs low pulse can reset fault conditions. |
| 34 | INHA | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 35 | INLA | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 36 | INHB | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 37 | INLB | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 38 | INHC | input | High-side gate driver control input that controls the output of the high-side gate driver. |
| 39 | INLC | input | Low-side gate driver control input that controls the output of the low-side gate driver. |
| 40 | DVDD | power_out | 5-V internal regulator output; connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between DVDD and DGND, and it can source up to 10 mA externally. |
| 41 | DGND | power_in | Device digital ground that must be connected to system ground. |
| 42 | SW | output | Buck switch node; connect to an inductor, diode, and the CB bootstrap capacitor. |
| 43 | VIN | power_in | Buck regulator power supply input; place a X5R or X7R, VM-rated ceramic capacitor between VIN and GND. |
| 44 | VCC | power_out | 7-V internal regulator output that supplies the buck switch gate; connect a X5R or X7R, 0.47-µF, 16-V ceramic capacitor between VCC and GND. |
| 45 | BST | power_out | Buck regulator bootstrap input; connect a X5R or X7R, 0.01-µF, 16-V capacitor between BST and SW. |
| 46 | RCL | input | Current limit off-time set input; connect a resistor between RCL and GND. |
| 47 | RT/SD | input | On-time set and remote shutdown input; connect a resistor between RT/SD and VIN. |
| 48 | FB | input | Buck feedback input; a resistor divider from the buck post-inductor output to this pin sets the buck output voltage. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Motor Driver ICs |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DRV8350RSRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
drv8350rsrgzr-etched.step/drv8350rsrgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8350rsrgzr.step/drv8350rsrgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (101 pp, sha256
4ab34376642b461e, retrieved 2026-10-11, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).