component
DRV8323SRTAT
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
Publish 0.1.0
10 files changed
+13976
docs/drv8323srtat-datasheet.pdfadded⋯ 1 unchanged line ⋯
docs/hero.pngadded⋯ 1 unchanged line ⋯
drv8323srtat.glbadded⋯ 1 unchanged line ⋯
drv8323srtat.kicad_modadded+685@@ -0,0 +1,685 @@+(footprint "QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm"+ (version 20260206)+ (generator "kicad-footprint-generator")+ (layer "F.Cu")+ (descr "QFN, 40 Pin (http://ww1.microchip.com/downloads/en/PackagingSpec/00000049BQ.pdf#page=295)")+ (tags "QFN NoLead")+ (property "Reference" "REF**"+ (at 0 -4.3 0)+ (layer "F.SilkS")+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (property "Value" "QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm"+ (at 0 4.3 0)+ (layer "F.Fab")+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (property "KiLib_Generator" "package/no_lead"+ (at 0 0 0)+ (layer "F.SilkS")+ (hide yes)+ (effects+ (font+ (size 1 1)+ (thickness 0.15)+ )+ )+ )+ (attr smd)+ (duplicate_pad_numbers_are_jumpers no)+ (fp_line+ (start -3.11 -3.11)+ (end -2.635 -3.11)+ (stroke+ (width 0.12)+ (type solid)+ )+ (layer "F.SilkS")+ )+ (fp_line+ (start -3.11 -2.635)+ (end -3.11 -3.11)+ (stroke+ (width 0.12)+ (type solid)+ )+ (layer "F.SilkS")+ )+ (fp_line+ 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drv8323srtat.kicad_symadded+177@@ -0,0 +1,177 @@+(kicad_symbol_lib (version 20211014) (generator ds2sf_rect)+ (symbol "DRV8323SRTAT" (in_bom yes) (on_board yes)+ (property "Reference" "U" (at 0 30.48 0) (effects (font (size 1.27 1.27))))+ (property "Value" "DRV8323SRTAT" (at 0 -30.48 0) (effects (font (size 1.27 1.27))))+ (property "Footprint" "" (at 0 0 0) (effects (font (size 1.27 1.27)) hide))+ (symbol "DRV8323SRTAT_0_1"+ (rectangle (start -12.70 27.94) (end 12.70 -27.94)+ (stroke (width 0.254) (type default)) (fill (type background)))+ )+ (symbol "DRV8323SRTAT_1_1"+ (pin power_in line (at -17.78 25.40 0) (length 5.08)+ (name "CPL" (effects (font (size 1.27 1.27))))+ (number "1" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at -17.78 22.86 0) (length 5.08)+ (name "CPH" (effects (font (size 1.27 1.27))))+ (number "2" (effects (font (size 1.27 1.27))))+ )+ (pin power_in line (at -17.78 20.32 0) (length 5.08)+ (name "VCP" (effects (font (size 1.27 1.27))))+ (number "3" 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name="DRV8323SRTAT">+ <wire x1="-12.7" y1="27.94" x2="12.7" y2="27.94" width="0.254" layer="94"/>+ <wire x1="12.7" y1="27.94" x2="12.7" y2="-27.94" width="0.254" layer="94"/>+ <wire x1="12.7" y1="-27.94" x2="-12.7" y2="-27.94" width="0.254" layer="94"/>+ <wire x1="-12.7" y1="-27.94" x2="-12.7" y2="27.94" width="0.254" layer="94"/>+ <text x="0.0000" y="30.4800" size="1.27" layer="95" align="center">>NAME</text>+ <text x="0.0000" y="-30.4800" size="1.27" layer="96" align="center">>VALUE</text>+ <pin name="CPL" x="-17.78" y="25.4" length="middle" direction="pwr"/>+ <pin name="CPH" x="-17.78" y="22.86" length="middle" direction="pwr"/>+ <pin name="VCP" x="-17.78" y="20.32" length="middle" direction="pwr"/>+ <pin name="VM" x="-17.78" y="17.78" length="middle" direction="pwr"/>+ <pin name="VDRAIN" x="-17.78" y="15.24" length="middle" direction="in"/>+ <pin name="GHA" x="-17.78" y="12.7" length="middle" direction="out"/>+ <pin name="SHA" x="-17.78" y="10.16" length="middle" direction="io"/>+ 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<pin name="PAD" x="17.78" y="22.86" length="middle" direction="pas" rot="R180"/>+ <pin name="PGND" x="17.78" y="20.32" length="middle" direction="pwr" rot="R180"/>+ <pin name="INLC" x="17.78" y="17.78" length="middle" direction="in" rot="R180"/>+ <pin name="INHC" x="17.78" y="15.24" length="middle" direction="in" rot="R180"/>+ <pin name="INLB" x="17.78" y="12.7" length="middle" direction="in" rot="R180"/>+ <pin name="INHB" x="17.78" y="10.16" length="middle" direction="in" rot="R180"/>+ <pin name="INLA" x="17.78" y="7.62" length="middle" direction="in" rot="R180"/>+ <pin name="INHA" x="17.78" y="5.08" length="middle" direction="in" rot="R180"/>+ <pin name="DVDD" x="17.78" y="2.54" length="middle" direction="pwr" rot="R180"/>+ <pin name="AGND" x="17.78" y="0" length="middle" direction="pwr" rot="R180"/>+ <pin name="CAL" x="17.78" y="-2.54" length="middle" direction="in" rot="R180"/>+ <pin name="ENABLE" x="17.78" y="-5.08" length="middle" direction="in" rot="R180"/>+ <pin name="nSCS" x="17.78" y="-7.62" length="middle" direction="in" rot="R180"/>+ <pin name="SCLK" x="17.78" y="-10.16" length="middle" direction="in" rot="R180"/>+ <pin name="SDI" x="17.78" y="-12.7" length="middle" direction="in" rot="R180"/>+ <pin name="SDO" x="17.78" y="-15.24" length="middle" direction="hiz" rot="R180"/>+ <pin name="nFAULT" x="17.78" y="-17.78" length="middle" direction="hiz" rot="R180"/>+ <pin name="VREF" x="17.78" y="-20.32" length="middle" direction="pwr" rot="R180"/>+ <pin name="SOA" x="17.78" y="-22.86" length="middle" direction="out" rot="R180"/>+ <pin name="SOB" x="17.78" y="-25.4" length="middle" direction="out" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="DRV8323SRTAT" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="DRV8323SRTAT" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm">+ <connects>+ <connect gate="G$1" pin="CPL" pad="1"/>+ <connect gate="G$1" pin="CPH" pad="2"/>+ <connect gate="G$1" pin="VCP" pad="3"/>+ <connect gate="G$1" pin="VM" pad="4"/>+ <connect gate="G$1" pin="VDRAIN" pad="5"/>+ <connect gate="G$1" pin="GHA" pad="6"/>+ <connect gate="G$1" pin="SHA" pad="7"/>+ <connect gate="G$1" pin="GLA" pad="8"/>+ <connect gate="G$1" pin="SPA" pad="9"/>+ <connect gate="G$1" pin="SNA" pad="10"/>+ <connect gate="G$1" pin="SNB" pad="11"/>+ <connect gate="G$1" pin="SPB" pad="12"/>+ <connect gate="G$1" pin="GLB" pad="13"/>+ <connect gate="G$1" pin="SHB" pad="14"/>+ <connect gate="G$1" pin="GHB" pad="15"/>+ <connect gate="G$1" pin="GHC" pad="16"/>+ <connect gate="G$1" pin="SHC" pad="17"/>+ <connect gate="G$1" pin="GLC" pad="18"/>+ <connect gate="G$1" pin="SPC" pad="19"/>+ <connect gate="G$1" pin="SNC" pad="20"/>+ <connect gate="G$1" pin="SOC" pad="21"/>+ <connect gate="G$1" pin="PAD" pad="41"/>+ <connect gate="G$1" pin="PGND" pad="40"/>+ <connect gate="G$1" pin="INLC" pad="39"/>+ <connect gate="G$1" pin="INHC" pad="38"/>+ <connect gate="G$1" pin="INLB" pad="37"/>+ <connect gate="G$1" pin="INHB" pad="36"/>+ <connect gate="G$1" pin="INLA" pad="35"/>+ <connect gate="G$1" pin="INHA" pad="34"/>+ <connect gate="G$1" pin="DVDD" pad="33"/>+ <connect gate="G$1" pin="AGND" pad="32"/>+ <connect gate="G$1" pin="CAL" pad="31"/>+ <connect gate="G$1" pin="ENABLE" pad="30"/>+ <connect gate="G$1" pin="nSCS" pad="29"/>+ <connect gate="G$1" pin="SCLK" pad="28"/>+ <connect gate="G$1" pin="SDI" pad="27"/>+ <connect gate="G$1" pin="SDO" pad="26"/>+ <connect gate="G$1" pin="nFAULT" pad="25"/>+ <connect gate="G$1" pin="VREF" pad="24"/>+ <connect gate="G$1" pin="SOA" pad="23"/>+ <connect gate="G$1" pin="SOB" pad="22"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
drv8323srtat.stepadded+12532@@ -0,0 +1,12532 @@+ISO-10303-21; +HEADER; +/* QFN-40-1EP_6x6mm_Pitch0.5mm.step 3D STEP model for use in ECAD systems + * Copyright (C) 2017, kicad StepUp + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + * + * As a special exception, if you create a design which uses this symbol, + * and embed this symbol or unaltered portions of this symbol into the design, + * this symbol does not by itself cause the resulting design to be covered by + * the GNU General Public License. + * This exception does not however invalidate any other reasons why the design + * itself might be covered by the GNU General Public License. + * If you modify this symbol, you may extend this exception to your version of the symbol, + * but you are not obligated to do so. + * If you do not wish to do so, delete this exception statement from your version + * Risk disclaimer + * *USE 3D CAD DATA AT YOUR OWN RISK* + * *DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.* + * + */ + +FILE_DESCRIPTION( +/* description */ ('model of QFN-40-1EP_6x6mm_Pitch0.5mm'), +/* implementation_level */ '2;1'); + +FILE_NAME( +/* name */ 'QFN-40-1EP_6x6mm_Pitch0.5mm.step', +/* time_stamp */ '2017-03-23T11:14:12', +/* author */ ('kicad StepUp','ksu'), +/* organization */ ('FreeCAD'), +/* preprocessor_version */ 'OCC', +/* originating_system */ 'kicad StepUp', +/* authorisation */ ''); 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package.jsonadded+349@@ -0,0 +1,349 @@+{+ "slug": "drv8323srtat",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8323srtat",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8323srtat.kicad_sym",+ "drv8323srtat.kicad_mod",+ "drv8323srtat.glb",+ "drv8323srtat.step",+ "drv8323srtat.lbr",+ "docs/hero.png",+ "docs/drv8323srtat-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8323SRTAT",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Motor Driver ICs",+ "subcategory": "Brushless DC (BLDC) Motor Driver",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8323",+ "parts": {+ "symbol": "drv8323srtat.kicad_sym",+ "footprint": "drv8323srtat.kicad_mod",+ "model_3d": "drv8323srtat-etched.glb",+ "model_3d_plain": "drv8323srtat.glb",+ "model_3d_step": "drv8323srtat-etched.step",+ "model_3d_step_plain": "drv8323srtat.step",+ "lbr": "drv8323srtat.lbr"+ },+ "distributor_links": {+ "lcsc": "C2150452",+ "digikey": "296-47095-2-ND",+ "mouser": "595-DRV8323SRTAT"+ },+ "distributor_check": {+ "checked_at": "2026-10-01T00:46:40Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-47095-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-DRV8323SRTAT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump negative switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump positive switch node; connect 47nF X5R or X7R ceramic capacitor rated at VM between CPH and CPL."+ },+ {+ "number": "3",+ "name": "VCP",+ "type": "power_in",+ "description": "Charge pump output (\u2248VM + 11V); connect 1\u00b5F 25V X5R or X7R capacitor between VCP and VM."+ },+ {+ "number": "4",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input, 6V to 60V; connect 0.1\u00b5F and \u226510\u00b5F bulk capacitors to PGND."+ },+ {+ "number": "5",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain common point input for VDS overvoltage monitor."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side source pin phase A; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output phase A; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase A; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Current sense amplifier negative input phase A; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Current sense amplifier negative input phase B; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase B; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side source pin phase B; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output phase B; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side source pin phase C; VDS monitor input and gate driver sink current output path from MOSFET source."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output phase C; supports 1A peak pull current and 2A peak sink current to MOSFET gate."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low-side shunt amplifier positive input phase C; connect to low-side MOSFET source and sense resistor high side."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Current sense amplifier negative input phase C; connect to low side of sense resistor or PGND if unused."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Current sense amplifier output phase C; leave open if current sense amplifier not used."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Current sense amplifier output phase B; leave open if current sense amplifier not used."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Current sense amplifier output phase A; leave open if current sense amplifier not used."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_in",+ "description": "Current sense amplifier power input and reference (3V to 5.5V); connect 0.1\u00b5F 6.3V capacitor to AGND."+ },+ {+ "number": "25",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator open-drain output pulled low during fault condition; requires external pull-up resistor."+ },+ {+ "number": "26",+ "name": "SDO",+ "type": "tri_state",+ "description": "Serial data output open-drain; shifts out on SCLK rising edge; requires external pull-up resistor."+ },+ {+ "number": "27",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input; data captured on SCLK falling edge for SPI register read/write operations."+ },+ {+ "number": "28",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input; clock signal for SPI communication determining SDI capture and SDO propagation."+ },+ {+ "number": "29",+ "name": "nSCS",+ "type": "input",+ "description": "Serial chip select; logic low level enables SPI interface communication with the device."+ },+ {+ "number": "30",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input; logic low enters low-power sleep mode; 8\u00b5s to 40\u00b5s pulse clears faults without sleep."+ },+ {+ "number": "31",+ "name": "CAL",+ "type": "input",+ "description": "Amplifier calibration input; set logic high to short amplifier inputs and execute automatic offset voltage calibration."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground connection; must be externally connected to PGND for proper operation."+ },+ {+ "number": "33",+ "name": "DVDD",+ "type": "power_in",+ "description": "3.3V internal regulator output (30mA maximum); connect 1\u00b5F 6.3V X5R or X7R capacitor to AGND."+ },+ {+ "number": "34",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input phase A; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "35",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input phase A; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "36",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input phase B; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "37",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input phase B; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "38",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input phase C; controls high-side gate driver output in 6x PWM mode."+ },+ {+ "number": "39",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input phase C; controls low-side gate driver output in 6x PWM mode."+ },+ {+ "number": "40",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground; serves as low-side gate driver current return path; must be externally connected to AGND."+ },+ {+ "number": "41",+ "name": "PAD",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 57,+ "cost_usd": 0.5124,+ "at": "2026-10-01T00:46:21"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323",+ "pages": 95,+ "sha256": "98e62c0c61f99755",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ }+}
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