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DRV8323RSRGZT

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Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8323RSRGZT

Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-48-EP(7x7)

DRV8323RSRGZT from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB input Buck regulator feedback input for setting output voltage with external resistor divider.
2 PGND power_in Device power ground and return path for low-side MOSFET gate drive current; must be connected externally to AGND and BGND.
3 CPL power_in Charge pump switch node; connect X5R/X7R 47nF VM-rated capacitor between CPL and CPH.
4 CPH power_in Charge pump switch node; connect X5R/X7R 47nF VM-rated capacitor between CPH and CPL.
5 VCP power_in Charge pump output voltage; connect X5R/X7R 1µF 25V capacitor between VCP and VM.
6 VM power_in Gate driver power supply input for motor power and VDRAIN connection; connect 0.1µF/≥10µF VM-rated capacitor to PGND.
7 VDRAIN input High-side MOSFET drain sense input for VDS monitor at common drain point.
8 GHA output High-side gate driver output A for N-channel MOSFET gate connection.
9 SHA bidirectional High-side source pin connected to high-side MOSFET source; VDS monitor input and gate driver sink current output.
10 GLA output Low-side gate driver output A for N-channel MOSFET gate connection.
11 SPA input Low-side shunt amplifier input monitoring MOSFET source; connect to source and current sense resistor high side.
12 SNA input Current sense amplifier A input at low side of sense resistor; connect to PGND if CSA unused.
13 SNB input Current sense amplifier B input at low side of sense resistor; connect to PGND if CSA unused.
14 SPB input Low-side shunt amplifier B input monitoring MOSFET source; connect to source and current sense resistor high side.
15 GLB output Low-side gate driver output B for N-channel MOSFET gate connection.
16 SHB bidirectional High-side source pin B connected to high-side MOSFET source; VDS monitor input and gate driver sink current output.
17 GHB output High-side gate driver output B for N-channel MOSFET gate connection.
18 GHC output High-side gate driver output C for N-channel MOSFET gate connection.
19 SHC bidirectional High-side source pin C connected to high-side MOSFET source; VDS monitor input and gate driver sink current output.
20 GLC output Low-side gate driver output C for N-channel MOSFET gate connection.
21 SPC input Low-side shunt amplifier C input monitoring MOSFET source; connect to source and current sense resistor high side.
22 SNC input Current sense amplifier C input at low side of sense resistor; connect to PGND if CSA unused.
23 SOC output Current sense amplifier C output for current measurement; leave open if CSA unused.
24 SOB output Current sense amplifier B output for current measurement; leave open if CSA unused.
25 SOA output Current sense amplifier A output for current measurement; leave open if CSA unused.
26 VREF power_in Current sense amplifier power supply and reference voltage; connect X5R/X7R 0.1µF 6.3V capacitor to AGND.
27 DGND power_in Device digital ground connected to system ground.
28 nFAULT tri_state Fault indicator open-drain output pulled low during fault; requires external pull-up resistor.
29 SDO tri_state Serial data output open-drain on SCLK rising edge; requires external pull-up resistor for SPI interface.
30 SDI input Serial data input captured on SCLK falling edge for SPI interface.
31 SCLK input Serial clock input for SPI data capture on rising/falling edges.
32 nSCS input Serial chip select input; logic low enables SPI communication.
33 ENABLE input Gate driver enable input; logic low enters sleep mode; 8-40µs low pulse resets faults without sleep.
34 CAL input Amplifier calibration input; set high to short amplifier inputs and perform automatic offset voltage calibration.
35 AGND power_in Device analog ground connected to system ground; must be externally connected to BGND and PGND.
36 DVDD power_in 3.3V internal regulator output with 30mA available; connect X5R/X7R 1µF 6.3V capacitor to AGND.
37 INHA input High-side gate driver control input A for 6x PWM mode.
38 INLA input Low-side gate driver control input A for 6x PWM mode.
39 INHB input High-side gate driver control input B for 6x PWM mode.
40 INLB input Low-side gate driver control input B for 6x PWM mode.
41 INHC input High-side gate driver control input C for 6x PWM mode.
42 INLC input Low-side gate driver control input C for 6x PWM mode.
43 BGND power_in Buck regulator ground connected to system ground; must be externally connected to AGND and PGND.
44 CB power_in Buck regulator bootstrap capacitor input; connect X5R/X7R 0.1µF 16V capacitor between CB and SW.
45 SW output Buck regulator switch node connected to inductor, diode, and CB bootstrap capacitor.
46 NC unconnected No internal connection; pin may be left floating or connected to system ground.
47 VIN power_in Buck regulator power supply input; connect X5R/X7R VM-rated capacitor between VIN and BGND.
48 nSHDN input Buck regulator shutdown input; pull below 1.25V to disable, leave floating to enable; high-voltage tolerant with internal pull-up.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-48-EP(7x7)
Category Motor Driver ICs
Pins 49

CAD (KiCad official)

  • Symbol: DRV8323RSRGZT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: drv8323rsrgzt-etched.step / drv8323rsrgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8323rsrgzt.step / drv8323rsrgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (98 pp, sha256 9c4eee0ec7239000, retrieved 2026-10-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF