component
DRV8323RHRGZR
Public Made by Adomby adom
Texas Instruments Gate Drivers, VQFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownDRV8323RHRGZR
Texas Instruments · Gate Drivers · VQFN-48-EP(7x7)
DRV8323RHRGZR from Texas Instruments, in a VQFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | FB | input | Buck regulator feedback input; a resistor divider from the buck inductor output sets the buck output voltage. |
| 2 | PGND | power_in | Device power ground; also serves as the low-side MOSFET gate-drive return path; must be externally connected to AGND and BGND. |
| 3 | CPL | passive | Charge pump negative switching node; connect an X5R or X7R, 47nF, VM-rated ceramic flying capacitor between CPH and CPL. |
| 4 | CPH | passive | Charge pump positive switching node; connect an X5R or X7R, 47nF, VM-rated ceramic flying capacitor between CPH and CPL. |
| 5 | VCP | power_out | Charge pump output; connect an X5R or X7R, 1µF, 25V ceramic capacitor between VCP and VM. |
| 6 | VM | power_in | Gate driver power supply input; connect to the motor supply and VDRAIN; bypass with an X5R/X7R 0.1µF VM-rated capacitor and a ≥10µF VM-rated bulk capacitor to PGND. |
| 7 | VDRAIN | input | High-side MOSFET drain sense input; connect to the common drain node of the high-side MOSFETs; this pin is an input to the VDS monitor. |
| 8 | GHA | output | High-side gate driver output (phase A); connect to the gate of the high-side power MOSFET. |
| 9 | SHA | bidirectional | High-side source pin (phase A); connects to the high-side power MOSFET source; input to the VDS monitor and sink-current output for the high-side gate driver. |
| 10 | GLA | output | Low-side gate driver output (phase A); connect to the gate of the low-side power MOSFET. |
| 11 | SPA | input | Low-side shunt amplifier input (phase A); VDS also monitors this as the low-side MOSFET negative input; connects to the low-side MOSFET source and the high side of the current-shunt resistor; connect to SNA if the CSA is unused. |
| 12 | SNA | input | Current sense amplifier input (phase A); connects to the low side of the current sense resistor; connect to PGND if the CSA is unused. |
| 13 | SNB | input | Current sense amplifier input (phase B); connects to the low side of the current sense resistor; connect to PGND if the CSA is unused. |
| 14 | SPB | input | Low-side shunt amplifier input (phase B); VDS also monitors this as the low-side MOSFET negative input; connects to the low-side MOSFET source and the high side of the current-shunt resistor; connect to SNB if the CSA is unused. |
| 15 | GLB | output | Low-side gate driver output (phase B); connect to the gate of the low-side power MOSFET. |
| 16 | SHB | bidirectional | High-side source pin (phase B); connects to the high-side power MOSFET source; input to the VDS monitor and sink-current output for the high-side gate driver. |
| 17 | GHB | output | High-side gate driver output (phase B); connect to the gate of the high-side power MOSFET. |
| 18 | GHC | output | High-side gate driver output (phase C); connect to the gate of the high-side power MOSFET. |
| 19 | SHC | bidirectional | High-side source pin (phase C); connects to the high-side power MOSFET source; input to the VDS monitor and sink-current output for the high-side gate driver. |
| 20 | GLC | output | Low-side gate driver output (phase C); connect to the gate of the low-side power MOSFET. |
| 21 | SPC | input | Low-side shunt amplifier input (phase C); VDS also monitors this as the low-side MOSFET negative input; connects to the low-side MOSFET source and the high side of the current-shunt resistor; connect to SNC if the CSA is unused. |
| 22 | SNC | input | Current sense amplifier input (phase C); connects to the low side of the current sense resistor; connect to PGND if the CSA is unused. |
| 23 | SOC | output | Current sense amplifier output (phase C); leave this pin unconnected if the CSA is unused. |
| 24 | SOB | output | Current sense amplifier output (phase B); leave this pin unconnected if the CSA is unused. |
| 25 | SOA | output | Current sense amplifier output (phase A); leave this pin unconnected if the CSA is unused. |
| 26 | VREF | power_in | Current sense amplifier power input and reference; connect an X5R or X7R, 0.1µF, 6.3V ceramic capacitor between VREF and AGND. |
| 27 | DGND | power_in | Device ground; connect to system ground. |
| 28 | nFAULT | output | Fault indicator output; this open-drain pin is driven to logic low during a fault event and requires an external pull-up resistor. |
| 29 | MODE | input | PWM input mode setting; 4-level input pin set by an external resistor (hardware interface device). |
| 30 | IDRIVE | input | Gate drive output current setting; 7-level input pin set by an external resistor (hardware interface device). |
| 31 | VDS | input | VDS monitor trip-point setting; 7-level input pin set by an external resistor (hardware interface device). |
| 32 | GAIN | input | Amplifier gain setting; 4-level input pin set by an external resistor (hardware interface device). |
| 33 | ENABLE | input | Gate driver enable; a logic low places the device into low-power sleep mode; an 8µs to 40µs low pulse can reset a fault condition without entering sleep mode. |
| 34 | CAL | input | Amplifier calibration input; set to logic high to internally short the amplifier inputs and perform automatic offset voltage calibration. |
| 35 | AGND | power_in | Device analog ground; connect to system ground; AGND must be externally connected to BGND and PGND. |
| 36 | DVDD | power_out | 3.3V internal regulator output; connect an X5R or X7R, 1µF, 6.3V ceramic capacitor between DVDD and AGND; the regulator can source up to 30mA externally. |
| 37 | INHA | input | High-side gate driver control input (phase A); in 6x PWM mode this pin controls the high-side gate driver output. |
| 38 | INLA | input | Low-side gate driver control input (phase A); in 6x PWM mode this pin controls the low-side gate driver output. |
| 39 | INHB | input | High-side gate driver control input (phase B); in 6x PWM mode this pin controls the high-side gate driver output. |
| 40 | INLB | input | Low-side gate driver control input (phase B); in 6x PWM mode this pin controls the low-side gate driver output. |
| 41 | INHC | input | High-side gate driver control input (phase C); in 6x PWM mode this pin controls the high-side gate driver output. |
| 42 | INLC | input | Low-side gate driver control input (phase C); in 6x PWM mode this pin controls the low-side gate driver output. |
| 43 | BGND | power_in | Buck regulator ground; connect to system ground; BGND must be externally connected to AGND and PGND. |
| 44 | CB | passive | Buck regulator bootstrap input; connect an X5R or X7R, 0.1µF, 16V capacitor between CB and SW. |
| 45 | SW | output | Buck regulator switch node; connect this pin to the inductor, diode, and the CB bootstrap capacitor. |
| 46 | NC | unconnected | No internal connection; this pin may be left floating or connected to system ground. |
| 47 | VIN | power_in | Buck regulator power supply input; place an X5R or X7R, VM-rated ceramic capacitor between VIN and BGND. |
| 48 | nSHDN | input | Buck shutdown input; a high-voltage tolerant enable/disable pin with an internal pull-up current source; pull below 1.25V to disable, float to enable; two resistor dividers can be used to establish an input UVLO. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-48-EP(7x7) |
| Category | Motor Driver ICs |
| Pins | 49 |
CAD (KiCad official)
- Symbol:
DRV8323RHRGZR - Footprint:
Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm - 3D model: VQFN-48-EP(7x7) (KiCad packages3D, STEP)
- 3D model files:
drv8323rhrgzr-etched.step/drv8323rhrgzr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8323rhrgzr.step/drv8323rhrgzr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (95 pp, sha256
98e62c0c61f99755, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).