component
DRV8323HRTAT
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8323HRTAT++**Texas Instruments** · Motor Driver ICs · WQFN-40-EP(6x6)++DRV8323HRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPL | power_in | Charge pump negative switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL. |+| 2 | CPH | power_in | Charge pump switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL pins. |+| 3 | VCP | power_out | Charge pump output; connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM pins. |+| 4 | VM | power_in | Gate driver power supply input 6V to 60V; connect to motor power supply and VDRAIN with X5R/X7R 0.1µF VM-rated and ≥10µF bulk capacitors. |+| 5 | VDRAIN | input | High-side MOSFET drain input; connect to the common point of high-side MOSFET drains for VDS monitor. |+| 6 | GHA | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |+| 7 | SHA | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |+| 8 | GLA | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |+| 9 | SPA | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNA if CSA unused. |+| 10 | SNA | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |+| 11 | SNB | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |+| 12 | SPB | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNB if CSA unused. |+| 13 | GLB | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |+| 14 | SHB | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |+| 15 | GHB | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |+| 16 | GHC | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |+| 17 | SHC | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |+| 18 | GLC | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |+| 19 | SPC | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNC if CSA unused. |+| 20 | SNC | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |+| 21 | SOC | output | Current sense amplifier output for phase C; keep unconnected if current sense amplifier CSA not used. |+| 22 | SOB | output | Current sense amplifier output for phase B; keep unconnected if current sense amplifier CSA not used. |+| 23 | SOA | output | Current sense amplifier output for phase A; keep unconnected if current sense amplifier CSA not used. |+| 24 | VREF | power_out | Current sense amplifier power input and reference 3V to 5.5V; connect X5R or X7R 0.1µF 6.3V ceramic capacitor between VREF and AGND. |+| 25 | nFAULT | tri_state | Fault indicator open-drain output pulled to logic low during fault condition; requires external pull-up resistor to logic supply. |+| 26 | MODE | input | PWM input mode setting 4-level input set by external resistor for 6x/3x/1x/Independent PWM mode selection. |+| 27 | IDRIVE | input | Gate driver output current setting 7-level input set by external resistor to select 10mA to 1A peak drive current. |+| 28 | VDS | input | VDS monitoring trip point setting 7-level input set by external resistor to select overcurrent threshold 0.06V to 1.88V. |+| 29 | GAIN | input | Amplifier gain setting 4-level input set by external resistor for current sense amplifier gain 5V/V to 40V/V selection. |+| 30 | ENABLE | input | Gate driver enable input; logic low enables low-power sleep mode, pulse 8µs to 40µs resets fault without sleep mode. |+| 31 | CAL | input | Amplifier calibration input; set to logic high to internally short amplifier inputs and perform automatic offset voltage calibration. |+| 32 | AGND | power_in | Device analog ground; connect to system ground with AGND externally connected to PGND. |+| 33 | DVDD | power_out | 3.3V internal regulator output with 30mA capacity; connect X5R or X7R 1µF 6.3V ceramic capacitor between DVDD and AGND. |+| 34 | INHA | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase A. |+| 35 | INLA | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase A. |+| 36 | INHB | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase B. |+| 37 | INLB | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase B. |+| 38 | INHC | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase C. |+| 39 | INLC | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase C. |+| 40 | PGND | power_in | Device power ground and low-side MOSFET gate driver return path; connect to system ground with PGND externally connected to AGND. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | WQFN-40-EP(6x6) |+| Category | Power Supply Chip |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8323HRTAT`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8323hrtat-etched.step` / `drv8323hrtat-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8323hrtat.step` / `drv8323hrtat.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-10-03, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8323hrtat-datasheet.pdf)
page.jsonadded+360@@ -0,0 +1,360 @@+{+ "slug": "drv8323hrtat",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Motor Driver ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "drv8323hrtat",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8323hrtat.kicad_sym",+ "drv8323hrtat.kicad_mod",+ "drv8323hrtat.glb",+ "drv8323hrtat.step",+ "drv8323hrtat.lbr",+ "docs/hero.png",+ "docs/drv8323hrtat-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "drv8323hrtat-hero.glb",+ "drv8323hrtat-hero.overlay.json"+ ],+ "component": {+ "mpn": "DRV8323HRTAT",+ "manufacturer": "Texas Instruments",+ "package": "WQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Power Supply Chip",+ "subcategory": "Motor Driver ICs",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8323",+ "parts": {+ "symbol": "drv8323hrtat.kicad_sym",+ "footprint": "drv8323hrtat.kicad_mod",+ "model_3d": "drv8323hrtat-hero.glb",+ "model_3d_plain": "drv8323hrtat.glb",+ "model_3d_step": "drv8323hrtat-etched.step",+ "model_3d_step_plain": "drv8323hrtat.step",+ "lbr": "drv8323hrtat.lbr"+ },+ "distributor_links": {+ "lcsc": 2150673,+ "digikey": "296-47094-2-ND",+ "mouser": "595-DRV8323HRTAT"+ },+ "distributor_check": {+ "checked_at": "2026-10-03T05:52:51Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-47094-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DRV8323HRTAT",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CPL",+ "type": "power_in",+ "description": "Charge pump negative switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "power_in",+ "description": "Charge pump switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL pins."+ },+ {+ "number": "3",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output; connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM pins."+ },+ {+ "number": "4",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input 6V to 60V; connect to motor power supply and VDRAIN with X5R/X7R 0.1µF VM-rated and ≥10µF bulk capacitors."+ },+ {+ "number": "5",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain input; connect to the common point of high-side MOSFET drains for VDS monitor."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "bidirectional",+ "description": "High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNA if CSA unused."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNB if CSA unused."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "bidirectional",+ "description": "High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "bidirectional",+ "description": "High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNC if CSA unused."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Current sense amplifier output for phase C; keep unconnected if current sense amplifier CSA not used."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Current sense amplifier output for phase B; keep unconnected if current sense amplifier CSA not used."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Current sense amplifier output for phase A; keep unconnected if current sense amplifier CSA not used."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_out",+ "description": "Current sense amplifier power input and reference 3V to 5.5V; connect X5R or X7R 0.1µF 6.3V ceramic capacitor between VREF and AGND."+ },+ {+ "number": "25",+ "name": "nFAULT",+ "type": "tri_state",+ "description": "Fault indicator open-drain output pulled to logic low during fault condition; requires external pull-up resistor to logic supply."+ },+ {+ "number": "26",+ "name": "MODE",+ "type": "input",+ "description": "PWM input mode setting 4-level input set by external resistor for 6x/3x/1x/Independent PWM mode selection."+ },+ {+ "number": "27",+ "name": "IDRIVE",+ "type": "input",+ "description": "Gate driver output current setting 7-level input set by external resistor to select 10mA to 1A peak drive current."+ },+ {+ "number": "28",+ "name": "VDS",+ "type": "input",+ "description": "VDS monitoring trip point setting 7-level input set by external resistor to select overcurrent threshold 0.06V to 1.88V."+ },+ {+ "number": "29",+ "name": "GAIN",+ "type": "input",+ "description": "Amplifier gain setting 4-level input set by external resistor for current sense amplifier gain 5V/V to 40V/V selection."+ },+ {+ "number": "30",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable input; logic low enables low-power sleep mode, pulse 8µs to 40µs resets fault without sleep mode."+ },+ {+ "number": "31",+ "name": "CAL",+ "type": "input",+ "description": "Amplifier calibration input; set to logic high to internally short amplifier inputs and perform automatic offset voltage calibration."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground; connect to system ground with AGND externally connected to PGND."+ },+ {+ "number": "33",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3V internal regulator output with 30mA capacity; connect X5R or X7R 1µF 6.3V ceramic capacitor between DVDD and AGND."+ },+ {+ "number": "34",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase A."+ },+ {+ "number": "35",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase A."+ },+ {+ "number": "36",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase B."+ },+ {+ "number": "37",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase B."+ },+ {+ "number": "38",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase C."+ },+ {+ "number": "39",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase C."+ },+ {+ "number": "40",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground and low-side MOSFET gate driver return path; connect to system ground with PGND externally connected to AGND."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: DRV8323HRTAT is marked as DRV8323H variant (hardware interface, no integrated buck regulator). The d",+ "exposed pad 41 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 57,+ "cost_usd": 0.5447,+ "at": "2026-10-03T05:52:18"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8323",+ "pages": 95,+ "sha256": "98e62c0c61f99755",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}