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DRV8323HRTAT
Public Made by Adomby adom
Texas Instruments Motor Driver ICs, WQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8323HRTAT
Texas Instruments · Motor Driver ICs · WQFN-40-EP(6x6)
DRV8323HRTAT from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPL | power_in | Charge pump negative switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL. |
| 2 | CPH | power_in | Charge pump switching node; connect X5R or X7R 47nF VM-rated ceramic capacitor between CPH and CPL pins. |
| 3 | VCP | power_out | Charge pump output; connect X5R or X7R 1µF 25V ceramic capacitor between VCP and VM pins. |
| 4 | VM | power_in | Gate driver power supply input 6V to 60V; connect to motor power supply and VDRAIN with X5R/X7R 0.1µF VM-rated and ≥10µF bulk capacitors. |
| 5 | VDRAIN | input | High-side MOSFET drain input; connect to the common point of high-side MOSFET drains for VDS monitor. |
| 6 | GHA | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |
| 7 | SHA | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |
| 8 | GLA | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |
| 9 | SPA | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNA if CSA unused. |
| 10 | SNA | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |
| 11 | SNB | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |
| 12 | SPB | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNB if CSA unused. |
| 13 | GLB | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |
| 14 | SHB | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |
| 15 | GHB | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |
| 16 | GHC | output | High-side gate driver output; connect to high-side power MOSFET gate with up to 1A peak current drive capability. |
| 17 | SHC | bidirectional | High-side source pin; connect to high-side MOSFET source for VDS monitoring and gate driver sink current return path. |
| 18 | GLC | output | Low-side gate driver output; connect to low-side power MOSFET gate with up to 2A peak sink current capability. |
| 19 | SPC | input | Low-side shunt amplifier input and VDS monitor negative input; connect to current shunt high side or SNC if CSA unused. |
| 20 | SNC | input | Current sense amplifier input; connect to current sampling resistor low side or PGND if CSA unused. |
| 21 | SOC | output | Current sense amplifier output for phase C; keep unconnected if current sense amplifier CSA not used. |
| 22 | SOB | output | Current sense amplifier output for phase B; keep unconnected if current sense amplifier CSA not used. |
| 23 | SOA | output | Current sense amplifier output for phase A; keep unconnected if current sense amplifier CSA not used. |
| 24 | VREF | power_out | Current sense amplifier power input and reference 3V to 5.5V; connect X5R or X7R 0.1µF 6.3V ceramic capacitor between VREF and AGND. |
| 25 | nFAULT | tri_state | Fault indicator open-drain output pulled to logic low during fault condition; requires external pull-up resistor to logic supply. |
| 26 | MODE | input | PWM input mode setting 4-level input set by external resistor for 6x/3x/1x/Independent PWM mode selection. |
| 27 | IDRIVE | input | Gate driver output current setting 7-level input set by external resistor to select 10mA to 1A peak drive current. |
| 28 | VDS | input | VDS monitoring trip point setting 7-level input set by external resistor to select overcurrent threshold 0.06V to 1.88V. |
| 29 | GAIN | input | Amplifier gain setting 4-level input set by external resistor for current sense amplifier gain 5V/V to 40V/V selection. |
| 30 | ENABLE | input | Gate driver enable input; logic low enables low-power sleep mode, pulse 8µs to 40µs resets fault without sleep mode. |
| 31 | CAL | input | Amplifier calibration input; set to logic high to internally short amplifier inputs and perform automatic offset voltage calibration. |
| 32 | AGND | power_in | Device analog ground; connect to system ground with AGND externally connected to PGND. |
| 33 | DVDD | power_out | 3.3V internal regulator output with 30mA capacity; connect X5R or X7R 1µF 6.3V ceramic capacitor between DVDD and AGND. |
| 34 | INHA | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase A. |
| 35 | INLA | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase A. |
| 36 | INHB | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase B. |
| 37 | INLB | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase B. |
| 38 | INHC | input | High-side gate driver control input; in 6x PWM mode, controls high-side gate driver output state for phase C. |
| 39 | INLC | input | Low-side gate driver control input; in 6x PWM mode, controls low-side gate driver output state for phase C. |
| 40 | PGND | power_in | Device power ground and low-side MOSFET gate driver return path; connect to system ground with PGND externally connected to AGND. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Power Supply Chip |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
DRV8323HRTAT - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
drv8323hrtat-etched.step/drv8323hrtat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8323hrtat.step/drv8323hrtat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (95 pp, sha256
98e62c0c61f99755, retrieved 2026-10-03, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).