# DRV8323HRTAR

**Texas Instruments** · Brushless DC (BLDC) Motor Driver · WQFN-40-EP(6x6)

DRV8323HRTAR from Texas Instruments, in a WQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPL | power_in | Charge pump switch node; connect 47nF X5R/X7R capacitor between CPH and CPL pins. |
| 2 | CPH | power_in | Charge pump switch node; connect 47nF X5R/X7R capacitor between CPH and CPL pins. |
| 3 | VCP | power_out | Charge pump output regulated to VVM + 11V; connect 1µF 25V X5R/X7R capacitor to VM pin. |
| 4 | VM | power_in | Gate driver power supply input, 6V to 60V operating range; connect to motor power and VDRAIN. |
| 5 | VDRAIN | input | High side MOSFET drain sensing input; connect to common drain point of high side MOSFETs for VDS over-current monitoring. |
| 6 | GHA | output | High side gate driver output for phase A; connect to high side N-channel MOSFET gate. |
| 7 | SHA | bidirectional | High side source pin for phase A; serves as VDS monitor input and gate driver sink current output. |
| 8 | GLA | output | Low side gate driver output for phase A; connect to low side N-channel MOSFET gate. |
| 9 | SPA | input | Low side shunt amplifier positive input for phase A; connect to RSENSE high side or leave open if CSA disabled. |
| 10 | SNA | input | Current sense amplifier negative input for phase A; connect to RSENSE low side or PGND if CSA unused. |
| 11 | SNB | input | Current sense amplifier negative input for phase B; connect to RSENSE low side or PGND if CSA unused. |
| 12 | SPB | input | Low side shunt amplifier positive input for phase B; connect to RSENSE high side or leave open if CSA disabled. |
| 13 | GLB | output | Low side gate driver output for phase B; connect to low side N-channel MOSFET gate. |
| 14 | SHB | bidirectional | High side source pin for phase B; serves as VDS monitor input and gate driver sink current output. |
| 15 | GHB | output | High side gate driver output for phase B; connect to high side N-channel MOSFET gate. |
| 16 | GHC | output | High side gate driver output for phase C; connect to high side N-channel MOSFET gate. |
| 17 | SHC | bidirectional | High side source pin for phase C; serves as VDS monitor input and gate driver sink current output. |
| 18 | GLC | output | Low side gate driver output for phase C; connect to low side N-channel MOSFET gate. |
| 19 | SPC | input | Low side shunt amplifier positive input for phase C; connect to RSENSE high side or leave open if CSA disabled. |
| 20 | SNC | input | Current sense amplifier negative input for phase C; connect to RSENSE low side or PGND if CSA unused. |
| 21 | SOC | output | Current sense amplifier output for phase C; output voltage proportional to sensed phase C current. |
| 22 | SOB | output | Current sense amplifier output for phase B; output voltage proportional to sensed phase B current. |
| 23 | SOA | output | Current sense amplifier output for phase A; output voltage proportional to sensed phase A current. |
| 24 | VREF | power_in | Current sense amplifier reference and power input, 3.3V to 5.5V; connect 0.1µF 6.3V capacitor to AGND. |
| 25 | nFAULT | tri_state | Fault status open drain output; pulled low when fault condition detected, requires external pull-up resistor. |
| 26 | MODE | input | PWM input mode setting via 4-level resistor configuration; selects 6x, 3x, 1x PWM or independent modes. |
| 27 | IDRIVE | input | Gate driver output current strength setting via 7-level external resistor configuration; 10mA to 1A pull, 20mA to 2A sink. |
| 28 | VDS | input | VDS over-current trip threshold setting via 7-level external resistor configuration; 0.06V to 1.88V range. |
| 29 | GAIN | input | Current sense amplifier gain setting via 4-level resistor configuration; selects 5V/V, 10V/V, 20V/V, or 40V/V. |
| 30 | ENABLE | input | Gate driver enable input; logic low enters sleep mode, logic high enables normal operation with 1ms wake-up time. |
| 31 | CAL | input | Current sense amplifier calibration input; set high to short inputs and perform auto offset voltage calibration. |
| 32 | AGND | power_in | Analog ground reference; must be externally connected to PGND and system ground. |
| 33 | DVDD | power_out | 3.3V internal regulator output, 30mA maximum load; connect 1µF 6.3V X5R/X7R capacitor to AGND. |
| 34 | INHA | input | High side PWM control input for phase A; used in 6x, 3x, and independent PWM modes. |
| 35 | INLA | input | Low side PWM control input for phase A; used in 6x, 3x, and independent PWM modes. |
| 36 | INHB | input | High side PWM control input for phase B; used in 6x, 3x, and independent PWM modes. |
| 37 | INLB | input | Low side PWM control input for phase B; used in 6x, 3x, and independent PWM modes. |
| 38 | INHC | input | High side PWM control input for phase C; controls direction in 1x PWM mode or regular control in other modes. |
| 39 | INLC | input | Low side PWM control input for phase C; enables brake function when pulled low in 1x PWM mode. |
| 40 | PGND | power_in | Power ground and low side gate driver reference; must be externally connected to AGND and system ground. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-40-EP(6x6) |
| Category | Motor Driver ICs |
| Pins | 41 |

## CAD (KiCad official)

- Symbol: `DRV8323HRTAR`
- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`
- 3D model: WQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files: `drv8323hrtar-etched.step` / `drv8323hrtar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8323hrtar.step` / `drv8323hrtar.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8323) (95 pp, sha256 `98e62c0c61f99755`, retrieved 2026-09-27, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8323hrtar-datasheet.pdf)