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DRV8311PRRWR

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Texas Instruments Motor Driver ICs, WQFN-24(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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DRV8311PRRWR

Texas Instruments · Motor Driver ICs · WQFN-24(3x3)

DRV8311PRRWR from Texas Instruments, in a WQFN-24(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 nFAULT output Open-drain fault indication output that is pulled logic-low on a fault condition and requires an external pullup to AVDD (5.1-kΩ recommended, 5-mA max sink).
2 CSAREF power_in Current sense amplifier power supply input and reference, bypassed with a X5R or X7R 0.1-µF, 6.3-V ceramic capacitor to AGND (2 to 3.6 V recommended).
3 SOC output Current sense amplifier output for OUTC.
4 SOB output Current sense amplifier output for OUTB.
5 SOA output Current sense amplifier output for OUTA.
6 CP power_out Charge pump output, with a X5R or X7R 0.1-µF, 16-V ceramic capacitor connected between CP and VM.
7 VIN_AVDD power_in Supply input for the AVDD regulator (3 to 20 V recommended), bypassed with a 0.1-µF ceramic capacitor and a >=10-µF bulk capacitor, both VIN_AVDD-rated.
8 VM power_in Motor power supply (3 to 20 V recommended, 24 V abs max) with a 0.1-µF ceramic bypass and a >=10-µF VM-rated bulk capacitor to PGND, plus 0.1-µF, 16-V between VM and CP.
9 PGND power_in Device power ground, connect to system ground.
10 OUTA output Half-bridge output A, connect to motor winding.
11 OUTB output Half-bridge output B, connect to motor winding.
12 OUTC output Half-bridge output C, connect to motor winding.
13 NC unconnected No connect, leave the pin floating.
14 AD1 input Address selection input for tSPI (only on tSPI device DRV8311P).
15 AD0 input Address selection input for tSPI (only on tSPI device DRV8311P).
16 AGND power_in Device analog ground, connect to system ground.
17 AVDD power_out 3.3-V regulator output that can source up to 100 mA externally, with a X5R or X7R 0.7-µF to 7-µF, 6.3-V ceramic capacitor between AVDD and AGND.
18 NC unconnected No connect, leave the pin floating.
19 PWM_SYNC input Connect to the MCU signal to synchronize the internally generated PWM signals to the MCU in PWM generation mode (only on DRV8311P).
20 nSCS input Serial chip select, a logic low enables serial interface communication.
21 SDO output Serial data output, with data shifted out on the rising edge of SCLK.
22 SDI input Serial data input, with data captured on the falling edge of SCLK.
23 SCLK input Serial clock input, with data shifted out on the rising edge and captured on the falling edge of SCLK.
24 nSLEEP input A logic low puts the device in low-power sleep mode, and a 15 to 50-µs low pulse resets fault conditions without entering sleep mode.
25 Thermal pad power_in Exposed thermal pad that must be connected to PGND.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24(3x3)
Category Power Supply Chip
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply pin voltage VM -0.3 24 V 7
AVDD regulator input pin voltage VIN_AVDD -0.3 24 V 7
Voltage difference between ground pins PGND, AGND -0.3 0.3 V 7
Charge pump voltage CP -0.3 V max VM + 6 V 7
Analog regulator output pin voltage AVDD -0.3 4 V 7
Logic pin input voltage -0.3 6 V INHx, INLx, nSCS, nSLEEP, SCLK, SDI, ADx, GAIN, MODE, SLEW, PWM_SYNC 7
Logic pin output voltage -0.3 6 V nFAULT, SDO 7
Open drain output current range 0 5 mA nFAULT 7
CSA reference supply input CSAREF -0.3 4 V 7
Current sense amplifier output SOx -0.3 4 V 7
Peak output current 5 A OUTA, OUTB, OUTC 7
Output pin voltage -1 V OUTA, OUTB, OUTC; max VM + 1 V or 24 V (whichever is smaller) 7
Ambient temperature TA -40 125 °C 7
Junction temperature TJ -40 150 °C 7
Storage temperature Tstg -65 150 °C 7
ESD HBM V(ESD) -1500 1500 V Human body model, ANSI/ESDA/JEDEC JS-001 7
ESD CDM V(ESD) -750 750 V Charged device model, ANSI/ESDA/JEDEC JS-002 7
Power supply voltage VVM 3 12 20 V 7
AVDD regulator input pin voltage VVIN_AVDD 3 12 20 V 7
Output PWM frequency fPWM 200 kHz OUTA, OUTB, OUTC 7
Peak output current IOUT 5 A OUTA, OUTB, OUTC 7
Logic input voltage VIN -0.1 5.5 V INHx, INLx, nSCS, nSLEEP, SCLK, SDI, ADx, GAIN, MODE, SLEW, PWM_SYNC 7
Open drain pullup voltage VOD -0.1 5.5 V nFAULT 7
Open drain output sink current IOD 5 mA nFAULT 7
CSA reference input voltage VCSAREF 2 3.6 V CSAREF 7
CSA reference input current ICSAREF 2.5 7.5 mA CSAREF 7
Operating ambient temperature TA -40 125 °C 8
Operating junction temperature TJ -40 150 °C 8
Junction-to-ambient thermal resistance RθJA 42.6 °C/W QFN (RRW) 24 pins 8
Junction-to-case (top) thermal resistance RθJC(top) 37.9 °C/W QFN (RRW) 24 pins 8
Junction-to-board thermal resistance RθJB 15.7 °C/W QFN (RRW) 24 pins 8
Junction-to-top characterization parameter ΨJT 0.5 °C/W QFN (RRW) 24 pins 8
Junction-to-board characterization parameter ΨJB 15.6 °C/W QFN (RRW) 24 pins 8
Junction-to-case (bottom) thermal resistance RθJC(bot) 4.8 °C/W QFN (RRW) 24 pins 8
VM sleep mode current IVMQ 1.5 3 µA VVM = 12 V, nSLEEP = 0, TA = 25 °C 8
VM sleep mode current IVMQ 9 µA nSLEEP = 0, TA = 125 °C 8
VM standby mode current IVMS 7 12 mA VVM = 12 V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25 °C 8
VM standby mode current IVMS 8 12 mA nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF' 8
VM operating mode current IVM 10 13 mA VVM = 12 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C 8
VM operating mode current IVM 12 14 mA VVM = 12 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C 8
VM operating mode current IVM 10 15 mA nSLEEP =1, fPWM = 25 kHz 8
VM operating mode current IVM 12 15 mA nSLEEP =1, fPWM = 200 kHz 8
Analog regulator voltage VAVDD 3.15 3.3 3.45 V VVM > 4V, VVIN_AVDD > 4.5V, 0 mA ≤ IAVDD ≤ 100 mA 8
Analog regulator voltage VAVDD 3 3.3 3.6 V VVM > 3.5V, 3.5V ≤VVIN_AVDD ≤ 4.5V, 0 mA ≤ IAVDD ≤ 35 mA 8
Analog regulator voltage VAVDD 2.2 3.4 V 2.5V ≤VVIN_AVDD ≤ 3.5V, 0 mA ≤ IAVDD ≤ 10 mA; typ column printed as VIN_AVDD-0.3 8
External analog regulator current limit IAVDD_LIM 148 200 250 mA 8
External analog regulator load IAVDD 100 mA VVM > 4V, VVIN_AVDD > 4.5V 9
External analog regulator load IAVDD 40 mA VVM < 4V, VVIN_AVDD > 4.5V 9
External analog regulator load IAVDD 35 mA VVM > 3.5V, 3.6V ≤VVIN_AVDD ≤ 4.5V 9
External analog regulator load IAVDD 20 mA VVM < 3.5V, 3.6V ≤VVIN_AVDD ≤ 4.5V 9
External analog regulator load IAVDD 10 mA 2.5V ≤VVIN_AVDD ≤ 3.6V 9
Capacitance on AVDD pin CAVDD 0.7 1 7 µF IAVDD ≤ 25 mA; 9
Capacitance on AVDD pin CAVDD 3.3 4.7 7 µF IAVDD ≥ 25 mA; 9
AVDD Output Voltage Regulation RAVDD -3 3 % VVIN_AVDD > 4.5V; IAVDD ≤ 20 mA; 9
AVDD Output Voltage Regulation RAVDD -2 2 % VVIN_AVDD > 4.5V; 20 mA ≤ IAVDD ≤ 40 mA; 9
Charge pump regulator voltage VVCP 3 5 5.6 V VCP with respect to VM 9
Wakeup time tWAKE 1 3 ms VVM > VUVLO, nSLEEP = 1 to Output ready 9
Wakeup time for CSA tWAKE_CSA 30 50 µs VCSAREF > VCSAREF_UV to SOx ready, when nSLEEP = 1 9
Turn-off time tSLEEP 100 200 µs nSLEEP = 0 to driver tri-stated 9
Reset Pulse time tRST 10 65 µs nSLEEP = 0 period to reset faults 9
Input logic high voltage VIH 1.65 5.5 V INHx, INLx, nSLEEP, SCLK, SDI 9
Input logic low voltage VIL 0 0.6 V INHx, INLx, nSLEEP, SCLK, SDI 9
Input logic hysteresis VHYS 100 300 660 mV INHx, INLx, nSLEEP, SCLK, SDI 9
Input logic low current IIL -1 1 µA VPIN (Pin Voltage) = 0 V 9
Input logic high current IIH 30 µA nSLEEP, VPIN (Pin Voltage) = 5 V 9
Input logic high current IIH 50 µA Other pins, VPIN (Pin Voltage) = 5 V 9
Input pulldown resistance RPD 230 300 kΩ nSLEEP 9
Input pulldown resistance RPD 160 200 kΩ Other pins 9

CAD (KiCad official)

  • Symbol: DRV8311PRRWR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm
  • 3D model: WQFN-24(3x3) (KiCad packages3D, STEP)
  • 3D model files: drv8311prrwr-etched.step / drv8311prrwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8311prrwr.step / drv8311prrwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (101 pp, sha256 2bb6bac1bbcd6cff, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF