component
DRV8311HRRWR
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, WQFN-24(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 9d ago |
| viewers | 9d ago |
| drv8311hrrwr-etched.glb | 9d ago |
| drv8311hrrwr-etched.step | 9d ago |
| drv8311hrrwr-hero.glb | 9d ago |
| drv8311hrrwr-hero.overlay.json | 9d ago |
| drv8311hrrwr.glb | 9d ago |
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| drv8311hrrwr.lbr | 9d ago |
| drv8311hrrwr.step | 9d ago |
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| README.md | 9d ago |
DRV8311HRRWR
Texas Instruments · Brushless DC (BLDC) Motor Driver · WQFN-24(3x3)
DRV8311HRRWR from Texas Instruments, in a WQFN-24(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | nFAULT | output | Open-drain fault indication output that is pulled logic-low on a fault condition and requires an external pullup to AVDD (5.1 kΩ recommended), with a maximum open-drain sink current of 5 mA. |
| 2 | CSAREF | power_in | Current sense amplifier power supply input and reference, operating at 2 V to 3.6 V, decoupled with a X5R or X7R 0.1-µF 6.3-V capacitor to AGND. |
| 3 | SOC | output | Current sense amplifier output for OUTC. |
| 4 | SOB | output | Current sense amplifier output for OUTB. |
| 5 | SOA | output | Current sense amplifier output for OUTA. |
| 6 | CP | power_out | Charge pump output, connected through a X5R or X7R 0.1-µF 16-V ceramic capacitor between CP and VM. |
| 7 | VIN_AVDD | power_in | Supply input for the AVDD regulator, rated 3 V to 20 V, bypassed to AGND with a 0.1-µF ceramic capacitor and a bulk capacitor of at least 10 µF. |
| 8 | VM | power_in | Motor supply pin, rated 3 V to 20 V recommended (24 V absolute maximum), bypassed to PGND with a 0.1-µF VM-rated ceramic capacitor and a bulk capacitor of at least 10 µF. |
| 9 | PGND | power_in | Device power ground that must be connected to system ground. |
| 10 | OUTA | output | Half-bridge output A that connects to the motor winding, with a peak output current rating of 5 A. |
| 11 | OUTB | output | Half-bridge output B that connects to the motor winding, with a peak output current rating of 5 A. |
| 12 | OUTC | output | Half-bridge output C that connects to the motor winding, with a peak output current rating of 5 A. |
| 13 | INHC | input | High-side driver control input for OUTC that sets the high-side MOSFET state in 6x or 3x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 14 | INHB | input | High-side driver control input for OUTB that sets the high-side MOSFET state in 6x or 3x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 15 | INHA | input | High-side driver control input for OUTA that sets the high-side MOSFET state in 6x or 3x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 16 | AGND | power_in | Device analog ground that must be connected to system ground. |
| 17 | AVDD | power_out | 3.3-V regulator output that requires a 0.7 µF to 7 µF 6.3-V X5R or X7R ceramic capacitor to AGND and can source up to 100 mA externally. |
| 18 | INLA | input | Low-side driver control input for OUTA that sets the low-side MOSFET state in 6x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 19 | INLB | input | Low-side driver control input for OUTB that sets the low-side MOSFET state in 6x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 20 | INLC | input | Low-side driver control input for OUTC that sets the low-side MOSFET state in 6x PWM mode, with logic input range -0.1 V to 5.5 V. |
| 21 | GAIN | input | Current sense amplifier gain select, a 4-level input set by an external resistor to AVDD or AGND (DRV8311H only). |
| 22 | SLEW | input | OUTx voltage slew rate select, a 4-level input set by an external resistor to AVDD or AGND (DRV8311H only). |
| 23 | MODE | input | PWM mode select, a 4-level input set by an external resistor to AVDD or AGND that is latched at power-up (DRV8311H only). |
| 24 | nSLEEP | input | Logic-low input that puts the device into low-power sleep mode, where a 15 µs to 50 µs low pulse resets faults without entering sleep (DRV8311H only). |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24(3x3) |
| Category | Motor Driver ICs |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage (VM) | VM | -0.3 | 24 | V | 7 | ||
| AVDD regulator input pin voltage (VIN_AVDD) | VIN_AVDD | -0.3 | 24 | V | 7 | ||
| Voltage difference between ground pins (PGND, AGND) | -0.3 | 0.3 | V | 7 | |||
| Charge pump voltage (CP) | CP | -0.3 | V | 7 | |||
| Analog regulator output pin voltage (AVDD) | AVDD | -0.3 | 4 | V | 7 | ||
| Logic pin input voltage (INHx, INLx, nSCS, nSLEEP, SCLK, SDI, ADx, GAIN, MODE, SLEW, PWM_SYNC) | -0.3 | 6 | V | 7 | |||
| Logic pin output voltage (nFAULT, SDO) | -0.3 | 6 | V | 7 | |||
| Open drain output current range (nFAULT) | 0 | 5 | mA | 7 | |||
| Current sense amplifier reference supply input (CSAREF) | CSAREF | -0.3 | 4 | V | 7 | ||
| Current sense amplifier output (SOx) | SOx | -0.3 | 4 | V | 7 | ||
| Peak output current (OUTA, OUTB, OUTC) | 5 | A | 7 | ||||
| Output pin voltage (OUTA, OUTB, OUTC) | -1 | V | 7 | ||||
| Ambient temperature | TA | -40 | 125 | °C | 7 | ||
| Junction temperature | TJ | -40 | 150 | °C | 7 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 7 | ||
| Power supply voltage | VVM | 3 | 12 | 20 | V | 7 | |
| AVDD regulator input pin voltage | VIN_AVDD | 3 | 12 | 20 | V | 7 | |
| Output PWM frequency | fPWM | 200 | kHz | OUTA, OUTB, OUTC | 7 | ||
| Peak output current | IOUT | 5 | A | OUTA, OUTB, OUTC | 7 | ||
| Logic input voltage | VIN | -0.1 | 5.5 | V | INHx, INLx, nSCS, nSLEEP, SCLK, SDI, ADx, GAIN, MODE, SLEW, PWM_SYNC | 7 | |
| Open drain pullup voltage (nFAULT) | VOD | -0.1 | 5.5 | V | 7 | ||
| Open drain output sink current (nFAULT) | IOD | 5 | mA | 7 | |||
| CSA reference input voltage | VCSAREF | 2 | 3.6 | V | CSAREF | 7 | |
| CSA reference input current | ICSAREF | 2.5 | 7.5 | mA | CSAREF | 7 | |
| Operating ambient temperature | TA | -40 | 125 | °C | 8 | ||
| Operating junction temperature | TJ | -40 | 150 | °C | 8 | ||
| VM sleep mode current | IVMQ | 1.5 | 3 | µA | VVM = 12 V, nSLEEP = 0, TA = 25 °C | 8 | |
| VM standby mode current | IVMS | 7 | 12 | mA | VVM = 12 V, nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF', TA = 25 °C | 8 | |
| VM standby mode current | IVMS | 8 | 12 | mA | nSLEEP = 1, INHx = INLx = 0, SPI = 'OFF' | 8 | |
| VM operating mode current | IVM | 10 | 13 | mA | VVM = 12 V, nSLEEP = 1, fPWM = 25 kHz, TA = 25 °C | 8 | |
| VM operating mode current | IVM | 12 | 14 | mA | VVM = 12 V, nSLEEP = 1, fPWM = 200 kHz, TA = 25 °C | 8 | |
| VM operating mode current | IVM | 10 | 15 | mA | nSLEEP = 1, fPWM = 25 kHz | 8 | |
| VM operating mode current | IVM | 12 | 15 | mA | nSLEEP = 1, fPWM = 200 kHz | 8 | |
| Analog regulator voltage | VAVDD | 3.15 | 3.3 | 3.45 | V | VVM > 4V, VVIN_AVDD > 4.5V, 0 mA ≤ IAVDD ≤ 100 mA | 8 |
| Analog regulator voltage | VAVDD | 3 | 3.3 | 3.6 | V | VVM > 3.5V, 3.5V ≤ VVIN_AVDD ≤ 4.5V, 0 mA ≤ IAVDD ≤ 35 mA | 8 |
| Analog regulator voltage | VAVDD | 2.2 | 3.4 | V | 2.5V ≤ VVIN_AVDD ≤ 3.5V, 0 mA ≤ IAVDD ≤ 10 mA | 8 | |
| External analog regulator current limit | IAVDD_LIM | 148 | 200 | 250 | mA | 8 | |
| Capacitance on AVDD pin | CAVDD | 0.7 | 1 | 7 | µF | IAVDD ≤ 25 mA; | 9 |
| Capacitance on AVDD pin | CAVDD | 3.3 | 4.7 | 7 | µF | IAVDD ≥ 25 mA; | 9 |
| AVDD output voltage regulation | RAVDD | -3 | 3 | % | VVIN_AVDD > 4.5V; IAVDD ≤ 20 mA; | 9 | |
| AVDD output voltage regulation | RAVDD | -2 | 2 | % | VVIN_AVDD > 4.5V; 20 mA ≤ IAVDD ≤ 40 mA; | 9 | |
| Charge pump regulator voltage | VVCP | 3 | 5 | 5.6 | V | VCP with respect to VM | 9 |
| Wakeup time | tWAKE | 1 | 3 | ms | VVM > VUVLO, nSLEEP = 1 to Output ready | 9 | |
| Wakeup time for CSA | tWAKE_CSA | 30 | 50 | µs | VCSAREF > VCSAREF_UV to SOx ready, when nSLEEP = 1 | 9 | |
| Turn-off time | tSLEEP | 100 | 200 | µs | nSLEEP = 0 to driver tri-stated | 9 | |
| Reset pulse time | tRST | 10 | 65 | µs | nSLEEP = 0 period to reset faults | 9 | |
| Input logic low voltage (INHx, INLx, nSLEEP, SCLK, SDI) | VIL | 0 | 0.6 | V | 9 | ||
| Input logic high voltage (INHx, INLx, nSLEEP, SCLK, SDI) | VIH | 1.65 | 5.5 | V | 9 | ||
| Input logic hysteresis (INHx, INLx, nSLEEP, SCLK, SDI) | VHYS | 100 | 300 | 660 | mV | 9 | |
| Input logic low current (INHx, INLx, nSLEEP, SCLK, SDI) | IIL | -1 | 1 | µA | VPIN (Pin Voltage) = 0 V | 9 | |
| Input pulldown resistance (nSLEEP) | RPD | 230 | 300 | kΩ | nSLEEP | 9 | |
| Input pulldown resistance (other pins) | RPD | 160 | 200 | kΩ | Other pins | 9 | |
| Four-level input pullup resistance (GAIN, MODE, SLEW) | RPU | 48 | 70 | kΩ | To AVDD | 9 | |
| Four-level input pulldown resistance (GAIN, MODE, SLEW) | RPD | 160 | 200 | kΩ | To AGND | 9 | |
| Junction-to-ambient thermal resistance | RθJA | 42.6 | °C/W | 8 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 37.9 | °C/W | 8 | |||
| Junction-to-board thermal resistance | RθJB | 15.7 | °C/W | 8 |
CAD (KiCad official)
- Symbol:
DRV8311HRRWR - Footprint:
Package_DFN_QFN:QFN-24-1EP_3x3mm_P0.4mm_EP1.75x1.6mm - 3D model: WQFN-24(3x3) (KiCad packages3D, STEP)
- 3D model files:
drv8311hrrwr-etched.step/drv8311hrrwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8311hrrwr.step/drv8311hrrwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (94 pp, sha256
175351398d6a15a5, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).