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Contents

README

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DRV8306HRSMR

Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-32-EP(4x4)

DRV8306HRSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPH passive Charge-pump switching node requiring 22-nF VM-rated ceramic capacitor between CPH and CPL pins.
2 VCP power_out Charge pump output with 1-µF 16-V capacitor to VM supplying 7 to 11.5 V at 12-38 V input.
3 VM power_in Gate driver supply input from 6 to 38 V with 0.1-µF bypass and 10-µF bulk capacitance to PGND.
4 VDRAIN input High-side MOSFET drain sense input for VDS overcurrent monitoring from common drain point.
5 GHA output High-side gate driver A output connected to phase A MOSFET gate.
6 SHA input High-side source sense input A from phase A MOSFET source.
7 GLA output Low-side gate driver A output connected to phase A MOSFET gate.
8 ISEN input Low-side current sense input from sense resistor with 0.225 to 0.275 V cycle-by-cycle current limit threshold.
9 GLB output Low-side gate driver B output connected to phase B MOSFET gate.
10 SHB input High-side source sense input B from phase B MOSFET source.
11 GHB output High-side gate driver B output connected to phase B MOSFET gate.
12 GHC output High-side gate driver C output connected to phase C MOSFET gate.
13 SHC input High-side source sense input C from phase C MOSFET source.
14 GLC output Low-side gate driver C output connected to phase C MOSFET gate.
15 HPC input Hall element positive input C with 50 mV differential detection and 20 to 40 mV hysteresis.
16 HNC input Hall element negative input C with 50 mV differential detection and 20 to 40 mV hysteresis.
17 HPB input Hall element positive input B with 50 mV differential detection and 20 to 40 mV hysteresis.
18 HNB input Hall element negative input B with 50 mV differential detection and 20 to 40 mV hysteresis.
19 HPA input Hall element positive input A with 50 mV differential detection and 20 to 40 mV hysteresis.
20 HNA input Hall element negative input A with 50 mV differential detection and 20 to 40 mV hysteresis.
21 nFAULT tri_state Open-drain fault indicator output pulled to logic low during VM UVLO, CPUV, VDS overcurrent, gate driver fault, or thermal shutdown conditions.
22 IDRIVE input Gate drive current setting as 7-level resistor-configured input from 15 mA to 150 mA source and 30 mA to 300 mA sink.
23 VDS input VDS overcurrent monitor trip threshold setting as 7-level resistor-configured input from 0.15 V to 1.8 V.
24 ENABLE input Gate driver enable input entering low-power sleep mode when logic low with 15 to 40-µs reset pulse for fault recovery.
25 AGND power_in Device analog ground connection to system ground.
26 DVDD power_out 3.3-V regulated output from internal LDO with 1-µF 6.3-V bypass capacitor sourcing 30 mA maximum external load current.
27 PWM input PWM input for trapezoidal commutation motor control from 0 to 5.5 V logic level supporting 100% duty cycle.
28 FGOUT tri_state Open-drain commutation frequency output signal derived from all three Hall sensor inputs for closed-loop speed control.
29 DIR input Motor direction selection input for clockwise or counterclockwise rotation with internal 100 kΩ pulldown resistor.
30 nBRAKE input Motor brake activation input pulled low to brake motor by disabling high-side and enabling low-side MOSFETs with internal pulldown.
31 PGND power_in Device power ground connection to system ground with 0.1-µF bypass capacitor to VM.
32 CPL passive Charge-pump switching node requiring 22-nF VM-rated ceramic capacitor between CPH and CPL pins.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(4x4)
Category Motor Driver ICs
Pins 33

CAD (KiCad official)

  • Symbol: DRV8306HRSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: drv8306hrsmr-etched.step / drv8306hrsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8306hrsmr.step / drv8306hrsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 5a55fde42c409c8a, retrieved 2026-09-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF