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DRV8304SRHAR

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Texas Instruments Gate Drivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DRV8304SRHAR

Texas Instruments · Gate Drivers · VQFN-40-EP(6x6)

DRV8304SRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CPL passive Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins.
2 CPH passive Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins.
3 VCP power_out Charge pump output. Connect a X5R or X7R 1-µF 16-V ceramic capacitor between VCP and VM pins.
4 VM power_in Gate driver power supply input 6 to 38 V. Connect to bridge power supply with 0.1-µF and ≥10-µF local bypass capacitance to PGND.
5 VDRAIN input High-side MOSFET drain sense input. Connect to common point of external MOSFET drains.
6 GHA output High-side gate driver output. Connect to gate of high-side power MOSFET.
7 SHA input High-side source sense input. Connect to high-side power MOSFET source.
8 GLA output Low-side gate driver output. Connect to gate of low-side power MOSFET.
9 SPA input Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor.
10 SNA input Shunt amplifier input. Connect to low-side of current shunt resistor.
11 SNB input Shunt amplifier input. Connect to low-side of current shunt resistor.
12 SPB input Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor.
13 GLB output Low-side gate driver output. Connect to gate of low-side power MOSFET.
14 SHB input High-side source sense input. Connect to high-side power MOSFET source.
15 GHB output High-side gate driver output. Connect to gate of high-side power MOSFET.
16 GHC output High-side gate driver output. Connect to gate of high-side power MOSFET.
17 SHC input High-side source sense input. Connect to high-side power MOSFET source.
18 GLC output Low-side gate driver output. Connect to gate of low-side power MOSFET.
19 SPC input Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor.
20 SNC input Shunt amplifier input. Connect to low-side of current shunt resistor.
21 SOC output Shunt amplifier output.
22 SOB output Shunt amplifier output.
23 SOA output Shunt amplifier output.
24 VREF power_out Shunt amplifier power supply input and reference. Connect 0.1-µF 6.3-V ceramic capacitor between VREF and AGND.
25 nFAULT output Fault indicator open-drain output pulled logic low during fault condition. Requires external pullup resistor.
26 SDO output Serial data output. Data shifted on rising edge of SCLK. Open-drain output requires external pullup resistor.
27 SDI input Serial data input. Data captured on falling edge of SCLK.
28 SCLK input Serial clock input. Serial data shifted and captured on corresponding rising and falling edges.
29 nSCS input Serial chip select. Logic low on this pin enables serial interface communication.
30 ENABLE input Gate driver enable. Logic low enters low-power sleep mode. 5 to 32-µs low pulse resets fault conditions.
31 CAL input Amplifier calibration input. Set logic high to internally short amplifier inputs and perform offset calibration.
32 AGND power_in Device analog ground. Connect to system ground.
33 DVDD power_out 3.3-V internal regulator output. Connect 1-µF 6.3-V ceramic capacitor between DVDD and AGND. Regulator sources up to 30 mA externally.
34 INHA input High-side gate driver control input. Controls output of high-side gate driver GHA.
35 INLA input Low-side gate driver control input. Controls output of low-side gate driver GLA.
36 INHB input High-side gate driver control input. Controls output of high-side gate driver GHB.
37 INLB input Low-side gate driver control input. Controls output of low-side gate driver GLB.
38 INHC input High-side gate driver control input. Controls output of high-side gate driver GHC.
39 INLC input Low-side gate driver control input. Controls output of low-side gate driver GLC.
40 PGND power_in Device power ground. Connect to system ground.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-40-EP(6x6)
Category Motor Driver ICs
Pins 41

CAD (KiCad official)

  • Symbol: DRV8304SRHAR
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: drv8304srhar-etched.step / drv8304srhar-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8304srhar.step / drv8304srhar.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (72 pp, sha256 0f41cab19ba9226b, retrieved 2026-10-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF