component
DRV8304SRHAR
Public Made by Adomby adom
Texas Instruments Gate Drivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+78@@ -0,0 +1,78 @@+# DRV8304SRHAR++**Texas Instruments** · Gate Drivers · VQFN-40-EP(6x6)++DRV8304SRHAR from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CPL | passive | Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins. |+| 2 | CPH | passive | Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins. |+| 3 | VCP | power_out | Charge pump output. Connect a X5R or X7R 1-µF 16-V ceramic capacitor between VCP and VM pins. |+| 4 | VM | power_in | Gate driver power supply input 6 to 38 V. Connect to bridge power supply with 0.1-µF and ≥10-µF local bypass capacitance to PGND. |+| 5 | VDRAIN | input | High-side MOSFET drain sense input. Connect to common point of external MOSFET drains. |+| 6 | GHA | output | High-side gate driver output. Connect to gate of high-side power MOSFET. |+| 7 | SHA | input | High-side source sense input. Connect to high-side power MOSFET source. |+| 8 | GLA | output | Low-side gate driver output. Connect to gate of low-side power MOSFET. |+| 9 | SPA | input | Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor. |+| 10 | SNA | input | Shunt amplifier input. Connect to low-side of current shunt resistor. |+| 11 | SNB | input | Shunt amplifier input. Connect to low-side of current shunt resistor. |+| 12 | SPB | input | Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor. |+| 13 | GLB | output | Low-side gate driver output. Connect to gate of low-side power MOSFET. |+| 14 | SHB | input | High-side source sense input. Connect to high-side power MOSFET source. |+| 15 | GHB | output | High-side gate driver output. Connect to gate of high-side power MOSFET. |+| 16 | GHC | output | High-side gate driver output. Connect to gate of high-side power MOSFET. |+| 17 | SHC | input | High-side source sense input. Connect to high-side power MOSFET source. |+| 18 | GLC | output | Low-side gate driver output. Connect to gate of low-side power MOSFET. |+| 19 | SPC | input | Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor. |+| 20 | SNC | input | Shunt amplifier input. Connect to low-side of current shunt resistor. |+| 21 | SOC | output | Shunt amplifier output. |+| 22 | SOB | output | Shunt amplifier output. |+| 23 | SOA | output | Shunt amplifier output. |+| 24 | VREF | power_out | Shunt amplifier power supply input and reference. Connect 0.1-µF 6.3-V ceramic capacitor between VREF and AGND. |+| 25 | nFAULT | output | Fault indicator open-drain output pulled logic low during fault condition. Requires external pullup resistor. |+| 26 | SDO | output | Serial data output. Data shifted on rising edge of SCLK. Open-drain output requires external pullup resistor. |+| 27 | SDI | input | Serial data input. Data captured on falling edge of SCLK. |+| 28 | SCLK | input | Serial clock input. Serial data shifted and captured on corresponding rising and falling edges. |+| 29 | nSCS | input | Serial chip select. Logic low on this pin enables serial interface communication. |+| 30 | ENABLE | input | Gate driver enable. Logic low enters low-power sleep mode. 5 to 32-µs low pulse resets fault conditions. |+| 31 | CAL | input | Amplifier calibration input. Set logic high to internally short amplifier inputs and perform offset calibration. |+| 32 | AGND | power_in | Device analog ground. Connect to system ground. |+| 33 | DVDD | power_out | 3.3-V internal regulator output. Connect 1-µF 6.3-V ceramic capacitor between DVDD and AGND. Regulator sources up to 30 mA externally. |+| 34 | INHA | input | High-side gate driver control input. Controls output of high-side gate driver GHA. |+| 35 | INLA | input | Low-side gate driver control input. Controls output of low-side gate driver GLA. |+| 36 | INHB | input | High-side gate driver control input. Controls output of high-side gate driver GHB. |+| 37 | INLB | input | Low-side gate driver control input. Controls output of low-side gate driver GLB. |+| 38 | INHC | input | High-side gate driver control input. Controls output of high-side gate driver GHC. |+| 39 | INLC | input | Low-side gate driver control input. Controls output of low-side gate driver GLC. |+| 40 | PGND | power_in | Device power ground. Connect to system ground. |+| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VQFN-40-EP(6x6) |+| Category | Motor Driver ICs |+| Pins | 41 |++## CAD (KiCad official)++- Symbol: `DRV8304SRHAR`+- Footprint: `Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm`+- 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)+- 3D model files: `drv8304srhar-etched.step` / `drv8304srhar-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8304srhar.step` / `drv8304srhar.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/ds/symlink/drv8304.pdf) (72 pp, sha256 `0f41cab19ba9226b`, retrieved 2026-10-07, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8304srhar-datasheet.pdf)
page.jsonadded+399@@ -0,0 +1,399 @@+{+ "slug": "drv8304srhar",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Gate Drivers, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8304srhar",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8304srhar.kicad_sym",+ "drv8304srhar.kicad_mod",+ "drv8304srhar.glb",+ "drv8304srhar.step",+ "drv8304srhar.lbr",+ "docs/hero.png",+ "docs/drv8304srhar-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "drv8304srhar-hero.glb",+ "drv8304srhar-hero.overlay.json"+ ],+ "component": {+ "mpn": "DRV8304SRHAR",+ "manufacturer": "Texas Instruments",+ "package": "VQFN-40-EP(6x6)",+ "pin_count": 41,+ "category": "Motor Driver ICs",+ "subcategory": "Gate Drivers",+ "datasheet": "https://www.ti.com/cn/lit/ds/symlink/drv8304.pdf",+ "parts": {+ "symbol": "drv8304srhar.kicad_sym",+ "footprint": "drv8304srhar.kicad_mod",+ "model_3d": "drv8304srhar-hero.glb",+ "model_3d_plain": "drv8304srhar.glb",+ "model_3d_step": "drv8304srhar-etched.step",+ "model_3d_step_plain": "drv8304srhar.step",+ "lbr": "drv8304srhar.lbr"+ },+ "distributor_links": {+ "lcsc": "C1849480",+ "digikey": "296-DRV8304SRHARTR-ND",+ "mouser": "595-DRV8304SRHAR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T08:28:30Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DRV8304SRHARTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DRV8304SRHAR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CPL",+ "type": "passive",+ "description": "Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins."+ },+ {+ "number": "2",+ "name": "CPH",+ "type": "passive",+ "description": "Charge pump switching node. Connect a X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins."+ },+ {+ "number": "3",+ "name": "VCP",+ "type": "power_out",+ "description": "Charge pump output. Connect a X5R or X7R 1-µF 16-V ceramic capacitor between VCP and VM pins."+ },+ {+ "number": "4",+ "name": "VM",+ "type": "power_in",+ "description": "Gate driver power supply input 6 to 38 V. Connect to bridge power supply with 0.1-µF and ≥10-µF local bypass capacitance to PGND."+ },+ {+ "number": "5",+ "name": "VDRAIN",+ "type": "input",+ "description": "High-side MOSFET drain sense input. Connect to common point of external MOSFET drains."+ },+ {+ "number": "6",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output. Connect to gate of high-side power MOSFET."+ },+ {+ "number": "7",+ "name": "SHA",+ "type": "input",+ "description": "High-side source sense input. Connect to high-side power MOSFET source."+ },+ {+ "number": "8",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output. Connect to gate of low-side power MOSFET."+ },+ {+ "number": "9",+ "name": "SPA",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor."+ },+ {+ "number": "10",+ "name": "SNA",+ "type": "input",+ "description": "Shunt amplifier input. Connect to low-side of current shunt resistor."+ },+ {+ "number": "11",+ "name": "SNB",+ "type": "input",+ "description": "Shunt amplifier input. Connect to low-side of current shunt resistor."+ },+ {+ "number": "12",+ "name": "SPB",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor."+ },+ {+ "number": "13",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output. Connect to gate of low-side power MOSFET."+ },+ {+ "number": "14",+ "name": "SHB",+ "type": "input",+ "description": "High-side source sense input. Connect to high-side power MOSFET source."+ },+ {+ "number": "15",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output. Connect to gate of high-side power MOSFET."+ },+ {+ "number": "16",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output. Connect to gate of high-side power MOSFET."+ },+ {+ "number": "17",+ "name": "SHC",+ "type": "input",+ "description": "High-side source sense input. Connect to high-side power MOSFET source."+ },+ {+ "number": "18",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output. Connect to gate of low-side power MOSFET."+ },+ {+ "number": "19",+ "name": "SPC",+ "type": "input",+ "description": "Low-side source sense and shunt amplifier input. Connect to low-side MOSFET source and high-side of current shunt resistor."+ },+ {+ "number": "20",+ "name": "SNC",+ "type": "input",+ "description": "Shunt amplifier input. Connect to low-side of current shunt resistor."+ },+ {+ "number": "21",+ "name": "SOC",+ "type": "output",+ "description": "Shunt amplifier output."+ },+ {+ "number": "22",+ "name": "SOB",+ "type": "output",+ "description": "Shunt amplifier output."+ },+ {+ "number": "23",+ "name": "SOA",+ "type": "output",+ "description": "Shunt amplifier output."+ },+ {+ "number": "24",+ "name": "VREF",+ "type": "power_out",+ "description": "Shunt amplifier power supply input and reference. Connect 0.1-µF 6.3-V ceramic capacitor between VREF and AGND."+ },+ {+ "number": "25",+ "name": "nFAULT",+ "type": "output",+ "description": "Fault indicator open-drain output pulled logic low during fault condition. Requires external pullup resistor."+ },+ {+ "number": "26",+ "name": "SDO",+ "type": "output",+ "description": "Serial data output. Data shifted on rising edge of SCLK. Open-drain output requires external pullup resistor."+ },+ {+ "number": "27",+ "name": "SDI",+ "type": "input",+ "description": "Serial data input. Data captured on falling edge of SCLK."+ },+ {+ "number": "28",+ "name": "SCLK",+ "type": "input",+ "description": "Serial clock input. Serial data shifted and captured on corresponding rising and falling edges."+ },+ {+ "number": "29",+ "name": "nSCS",+ "type": "input",+ "description": "Serial chip select. Logic low on this pin enables serial interface communication."+ },+ {+ "number": "30",+ "name": "ENABLE",+ "type": "input",+ "description": "Gate driver enable. Logic low enters low-power sleep mode. 5 to 32-µs low pulse resets fault conditions."+ },+ {+ "number": "31",+ "name": "CAL",+ "type": "input",+ "description": "Amplifier calibration input. Set logic high to internally short amplifier inputs and perform offset calibration."+ },+ {+ "number": "32",+ "name": "AGND",+ "type": "power_in",+ "description": "Device analog ground. Connect to system ground."+ },+ {+ "number": "33",+ "name": "DVDD",+ "type": "power_out",+ "description": "3.3-V internal regulator output. Connect 1-µF 6.3-V ceramic capacitor between DVDD and AGND. Regulator sources up to 30 mA externally."+ },+ {+ "number": "34",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input. Controls output of high-side gate driver GHA."+ },+ {+ "number": "35",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input. Controls output of low-side gate driver GLA."+ },+ {+ "number": "36",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input. Controls output of high-side gate driver GHB."+ },+ {+ "number": "37",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input. Controls output of low-side gate driver GLB."+ },+ {+ "number": "38",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input. Controls output of high-side gate driver GHC."+ },+ {+ "number": "39",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input. Controls output of low-side gate driver GLC."+ },+ {+ "number": "40",+ "name": "PGND",+ "type": "power_in",+ "description": "Device power ground. Connect to system ground."+ },+ {+ "number": "41",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Thermal pad (exposed die pad) is present on this package but no standard pin number is assigned to i",+ "exposed pad 41 added from the footprint"+ ],+ "pages_sent": 8,+ "cost_usd": 0.155,+ "at": "2026-10-07T08:28:13"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/ds/symlink/drv8304.pdf",+ "pages": 72,+ "sha256": "0f41cab19ba9226b",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 41,+ "described": 41,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "drv8304srhar.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "drv8304srhar-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 6,+ 1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "f8f69fd4a15dc0224de396305cf4a6e3ffcdc3e51e18fb202efbe8eb354cb0e4",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}