component
DRV8304HRHAT
Public Made by Adomby adom
Texas Instruments Brushless DC (BLDC) Motor Driver, VQFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownDRV8304HRHAT
Texas Instruments · Brushless DC (BLDC) Motor Driver · VQFN-40-EP(6x6)
DRV8304HRHAT from Texas Instruments, in a VQFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CPL | power_in | Charge pump switching node; connect X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins. |
| 2 | CPH | power_in | Charge pump switching node; connect X5R or X7R 22-nF VM-rated ceramic capacitor between CPH and CPL pins. |
| 3 | VCP | power_in | Charge pump output; connect X5R or X7R 1-µF 16-V ceramic capacitor between VCP and VM pins. |
| 4 | VM | power_in | Gate driver power supply input for 6 to 38 V bridge power supply; connect X5R or X7R 0.1-µF VM-rated ceramic and ≥10-µF local capacitance between VM and PGND pins. |
| 5 | VDRAIN | input | High-side MOSFET drain sense input; connect to common point of external MOSFET drains. |
| 6 | GHA | output | High-side gate driver output; connect to gate of high-side power MOSFET. |
| 7 | SHA | input | High-side source sense input; connect to high-side power MOSFET source. |
| 8 | GLA | output | Low-side gate driver output; connect to gate of low-side power MOSFET. |
| 9 | SPA | input | Low-side source sense and shunt amplifier input; connect to low-side power MOSFET source and high-side of current shunt resistor. |
| 10 | SNA | input | Shunt amplifier input; connect to low-side of current shunt resistor. |
| 11 | SNB | input | Shunt amplifier input; connect to low-side of current shunt resistor. |
| 12 | SPB | input | Low-side source sense and shunt amplifier input; connect to low-side power MOSFET source and high-side of current shunt resistor. |
| 13 | GLB | output | Low-side gate driver output; connect to gate of low-side power MOSFET. |
| 14 | SHB | input | High-side source sense input; connect to high-side power MOSFET source. |
| 15 | GHB | output | High-side gate driver output; connect to gate of high-side power MOSFET. |
| 16 | GHC | output | High-side gate driver output; connect to gate of high-side power MOSFET. |
| 17 | SHC | input | High-side source sense input; connect to high-side power MOSFET source. |
| 18 | GLC | output | Low-side gate driver output; connect to gate of low-side power MOSFET. |
| 19 | SPC | input | Low-side source sense and shunt amplifier input; connect to low-side power MOSFET source and high-side of current shunt resistor. |
| 20 | SNC | input | Shunt amplifier input; connect to low-side of current shunt resistor. |
| 21 | SOC | output | Shunt amplifier output. |
| 22 | SOB | output | Shunt amplifier output. |
| 23 | SOA | output | Shunt amplifier output. |
| 24 | VREF | power_in | Shunt amplifier power supply input and reference; connect X5R or X7R 0.1-µF 6.3-V ceramic capacitor between VREF and AGND pins. |
| 25 | nFAULT | tri_state | Fault indicator output pulled logic low during fault condition; requires external pullup resistor. |
| 26 | MODE | input | PWM input mode setting; 4-level input pin set by external resistor for 1x, 3x, 6x and independent PWM modes. |
| 27 | IDRIVE | input | Gate drive output current setting; 7-level input pin set by external resistor for peak pull current 15 to 150 mA and peak sink current 30 to 300 mA. |
| 28 | VDS | input | VDS monitor trip point setting; 7-level input pin set by external resistor. |
| 29 | GAIN | input | Amplifier gain setting; 4-level input pin set by external resistor for gains of 5, 10, 20, or 40 V/V. |
| 30 | ENABLE | input | Gate driver enable; logic low enters low power sleep mode; 5 to 32-µs low pulse can reset fault conditions. |
| 31 | CAL | input | Amplifier calibration input; set logic high to internally short amplifier inputs and perform offset calibration. |
| 32 | AGND | power_in | Device analog ground; connect to system ground. |
| 33 | DVDD | power_in | 3.3-V internal regulator output sourcing up to 30 mA externally; connect X5R or X7R 1-µF 6.3-V ceramic capacitor between DVDD and AGND pins. |
| 34 | INHA | input | High-side gate driver control input; controls output of high-side gate driver GHA. |
| 35 | INLA | input | Low-side gate driver control input; controls output of low-side gate driver GLA. |
| 36 | INHB | input | High-side gate driver control input; controls output of high-side gate driver GHB. |
| 37 | INLB | input | Low-side gate driver control input; controls output of low-side gate driver GLB. |
| 38 | INHC | input | High-side gate driver control input; controls output of high-side gate driver GHC. |
| 39 | INLC | input | Low-side gate driver control input; controls output of low-side gate driver GLC. |
| 40 | PGND | power_in | Device power ground; connect to system ground. |
| 41 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-40-EP(6x6) |
| Category | Motor Driver ICs |
| Pins | 41 |
CAD (KiCad official)
- Symbol:
DRV8304HRHAT - Footprint:
Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm - 3D model: VQFN-40-EP(6x6) (KiCad packages3D, STEP)
- 3D model files:
drv8304hrhat-etched.step/drv8304hrhat-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);drv8304hrhat.step/drv8304hrhat.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (66 pp, sha256
a05048e03d261307, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).