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DRV8300DIPWR
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Texas Instruments Gate Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+57@@ -0,0 +1,57 @@+# DRV8300DIPWR++**Texas Instruments** · Gate Drivers · TSSOP-20++DRV8300DIPWR from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | INHA | input | High-side gate driver control input for phase A; rated 0 to VGVDD logic levels. |+| 2 | INHB | input | High-side gate driver control input for phase B; rated 0 to VGVDD logic levels. |+| 3 | INHC | input | High-side gate driver control input for phase C; rated 0 to VGVDD logic levels. |+| 4 | INLA | input | Low-side gate driver control input for phase A; provides inverted output polarity to GLA in DRV8300DI variant. |+| 5 | INLB | input | Low-side gate driver control input for phase B; provides inverted output polarity to GLB in DRV8300DI variant. |+| 6 | INLC | input | Low-side gate driver control input for phase C; provides inverted output polarity to GLC in DRV8300DI variant. |+| 7 | GVDD | power_in | Gate driver power supply input, rated 5 to 20 V; requires 10 µF bypass capacitor to GND. |+| 8 | GND | power_in | Device ground reference. |+| 9 | GLC | output | Low-side gate driver output for phase C; provides 750 mA peak source and 1.5 A peak sink current. |+| 10 | GLB | output | Low-side gate driver output for phase B; provides 750 mA peak source and 1.5 A peak sink current. |+| 11 | GLA | output | Low-side gate driver output for phase A; provides 750 mA peak source and 1.5 A peak sink current. |+| 12 | SHC | input | High-side source sense input for phase C, connected to high-side MOSFET source; rated -22 to 110 V. |+| 13 | GHC | output | High-side gate driver output for phase C; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum. |+| 14 | BSTC | output | Bootstrap voltage output for phase C; connect capacitor between BSTC and SHC for high-side gate drive supply. |+| 15 | SHB | input | High-side source sense input for phase B, connected to high-side MOSFET source; rated -22 to 110 V. |+| 16 | GHB | output | High-side gate driver output for phase B; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum. |+| 17 | BSTB | output | Bootstrap voltage output for phase B; connect capacitor between BSTB and SHB for high-side gate drive supply. |+| 18 | SHA | input | High-side source sense input for phase A, connected to high-side MOSFET source; rated -22 to 110 V. |+| 19 | GHA | output | High-side gate driver output for phase A; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum. |+| 20 | BSTA | output | Bootstrap voltage output for phase A; connect capacitor between BSTA and SHA for high-side gate drive supply. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-20 |+| Category | Motor Driver ICs |+| Pins | 20 |++## CAD (KiCad official)++- Symbol: `DRV8300DIPWR`+- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`+- 3D model: TSSOP-20 (KiCad packages3D, STEP)+- 3D model files: `drv8300dipwr-etched.step` / `drv8300dipwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8300dipwr.step` / `drv8300dipwr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/drv8300) (35 pp, sha256 `ce0cba4354bb3566`, retrieved 2026-09-27, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/drv8300dipwr-datasheet.pdf)
page.jsonadded+228@@ -0,0 +1,228 @@+{+ "slug": "drv8300dipwr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Gate Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "motor driver ics",+ "drv8300dipwr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "drv8300dipwr.kicad_sym",+ "drv8300dipwr.kicad_mod",+ "drv8300dipwr.glb",+ "drv8300dipwr.step",+ "drv8300dipwr.lbr",+ "docs/hero.png",+ "docs/drv8300dipwr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "DRV8300DIPWR",+ "manufacturer": "Texas Instruments",+ "package": "TSSOP-20",+ "pin_count": 20,+ "category": "Motor Driver ICs",+ "subcategory": "Gate Drivers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/drv8300",+ "parts": {+ "symbol": "drv8300dipwr.kicad_sym",+ "footprint": "drv8300dipwr.kicad_mod",+ "model_3d": "drv8300dipwr-etched.glb",+ "model_3d_plain": "drv8300dipwr.glb",+ "model_3d_step": "drv8300dipwr-etched.step",+ "model_3d_step_plain": "drv8300dipwr.step",+ "lbr": "drv8300dipwr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2862908",+ "digikey": "296-DRV8300DIPWRTR-ND",+ "mouser": "595-DRV8300DIPWR"+ },+ "distributor_check": {+ "checked_at": "2026-09-27T05:50:52Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-DRV8300DIPWRTR-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-DRV8300DIPWR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "INHA",+ "type": "input",+ "description": "High-side gate driver control input for phase A; rated 0 to VGVDD logic levels."+ },+ {+ "number": "2",+ "name": "INHB",+ "type": "input",+ "description": "High-side gate driver control input for phase B; rated 0 to VGVDD logic levels."+ },+ {+ "number": "3",+ "name": "INHC",+ "type": "input",+ "description": "High-side gate driver control input for phase C; rated 0 to VGVDD logic levels."+ },+ {+ "number": "4",+ "name": "INLA",+ "type": "input",+ "description": "Low-side gate driver control input for phase A; provides inverted output polarity to GLA in DRV8300DI variant."+ },+ {+ "number": "5",+ "name": "INLB",+ "type": "input",+ "description": "Low-side gate driver control input for phase B; provides inverted output polarity to GLB in DRV8300DI variant."+ },+ {+ "number": "6",+ "name": "INLC",+ "type": "input",+ "description": "Low-side gate driver control input for phase C; provides inverted output polarity to GLC in DRV8300DI variant."+ },+ {+ "number": "7",+ "name": "GVDD",+ "type": "power_in",+ "description": "Gate driver power supply input, rated 5 to 20 V; requires 10 µF bypass capacitor to GND."+ },+ {+ "number": "8",+ "name": "GND",+ "type": "power_in",+ "description": "Device ground reference."+ },+ {+ "number": "9",+ "name": "GLC",+ "type": "output",+ "description": "Low-side gate driver output for phase C; provides 750 mA peak source and 1.5 A peak sink current."+ },+ {+ "number": "10",+ "name": "GLB",+ "type": "output",+ "description": "Low-side gate driver output for phase B; provides 750 mA peak source and 1.5 A peak sink current."+ },+ {+ "number": "11",+ "name": "GLA",+ "type": "output",+ "description": "Low-side gate driver output for phase A; provides 750 mA peak source and 1.5 A peak sink current."+ },+ {+ "number": "12",+ "name": "SHC",+ "type": "input",+ "description": "High-side source sense input for phase C, connected to high-side MOSFET source; rated -22 to 110 V."+ },+ {+ "number": "13",+ "name": "GHC",+ "type": "output",+ "description": "High-side gate driver output for phase C; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum."+ },+ {+ "number": "14",+ "name": "BSTC",+ "type": "output",+ "description": "Bootstrap voltage output for phase C; connect capacitor between BSTC and SHC for high-side gate drive supply."+ },+ {+ "number": "15",+ "name": "SHB",+ "type": "input",+ "description": "High-side source sense input for phase B, connected to high-side MOSFET source; rated -22 to 110 V."+ },+ {+ "number": "16",+ "name": "GHB",+ "type": "output",+ "description": "High-side gate driver output for phase B; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum."+ },+ {+ "number": "17",+ "name": "BSTB",+ "type": "output",+ "description": "Bootstrap voltage output for phase B; connect capacitor between BSTB and SHB for high-side gate drive supply."+ },+ {+ "number": "18",+ "name": "SHA",+ "type": "input",+ "description": "High-side source sense input for phase A, connected to high-side MOSFET source; rated -22 to 110 V."+ },+ {+ "number": "19",+ "name": "GHA",+ "type": "output",+ "description": "High-side gate driver output for phase A; provides 750 mA peak source and 1.5 A peak sink current, rated -22 to 125 V absolute maximum."+ },+ {+ "number": "20",+ "name": "BSTA",+ "type": "output",+ "description": "Bootstrap voltage output for phase A; connect capacitor between BSTA and SHA for high-side gate drive supply."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-haiku-4-5-20251001",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-4-6",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [],+ "pages_sent": 35,+ "cost_usd": 0.3918,+ "at": "2026-09-27T05:50:33"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/drv8300",+ "pages": 35,+ "sha256": "ce0cba4354bb3566",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 20,+ "described": 20,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}