component

DRV8256PPWPR

Public Made by Adom

by adom

Texas Instruments Motor Driver ICs, HTSSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower supply chipdrv8256ppwprfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers drv8256ppwpr: viewers · Ray 2d ago
drv8256ppwpr-etched.glb Publish 0.1.0 · Ray 2d ago
drv8256ppwpr-etched.step drv8256ppwpr: factory component page (tier=lcsc) · Ray 2d ago
drv8256ppwpr-hero.glb drv8256ppwpr: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
drv8256ppwpr-hero.overlay.json Publish 0.1.0 · Ray 2d ago
drv8256ppwpr.glb Publish 0.1.0 · Ray 2d ago
drv8256ppwpr.kicad_mod Publish 0.1.0 · Ray 2d ago
drv8256ppwpr.kicad_sym Publish 0.1.0 · Ray 2d ago
drv8256ppwpr.lbr Publish 0.1.0 · Ray 2d ago
drv8256ppwpr.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago

DRV8256PPWPR

Texas Instruments · Motor Driver ICs · HTSSOP-28

DRV8256PPWPR from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCP passive Charge pump output, connected to VM through an X7R 0.22µF 16V ceramic capacitor.
2 VM power_in Motor supply (4.5V to 48V), bypassed to PGND with a 0.01µF ceramic capacitor per VM pin rated for VM plus a bulk capacitor.
3 PGND power_in Power ground, connected to system ground.
4 OUT1 output Winding output connected to the motor winding; all OUT1 pins (4, 5, 10, 11) must be tied together with thick PCB traces.
5 OUT1 output Winding output connected to the motor winding; all OUT1 pins (4, 5, 10, 11) must be tied together with thick PCB traces.
6 OUT2 output Winding output connected to the motor winding; all OUT2 pins (6, 7, 8, 9) must be tied together with thick PCB traces.
7 OUT2 output Winding output connected to the motor winding; all OUT2 pins (6, 7, 8, 9) must be tied together with thick PCB traces.
8 OUT2 output Winding output connected to the motor winding; all OUT2 pins (6, 7, 8, 9) must be tied together with thick PCB traces.
9 OUT2 output Winding output connected to the motor winding; all OUT2 pins (6, 7, 8, 9) must be tied together with thick PCB traces.
10 OUT1 output Winding output connected to the motor winding; all OUT1 pins (4, 5, 10, 11) must be tied together with thick PCB traces.
11 OUT1 output Winding output connected to the motor winding; all OUT1 pins (4, 5, 10, 11) must be tied together with thick PCB traces.
12 PGND power_in Power ground, connected to system ground.
13 VM power_in Motor supply (4.5V to 48V), bypassed to PGND with a 0.01µF ceramic capacitor per VM pin rated for VM plus a bulk capacitor.
14 GND power_in Device ground, connected to system ground.
15 DVDD power_out Logic supply (nominal 5V, up to 2mA load) bypassed to GND with a 0.47µF to 1µF X7R ceramic capacitor rated 6.3V or 10V.
16 nFAULT output Fault indication, pulled logic low in a fault condition; open-drain output requiring an external pull-up resistor.
17 VREF power_in Reference voltage input that sets the full-scale chopping current of the H-bridge; both VREF pins must be connected together.
18 VREF power_in Reference voltage input that sets the full-scale chopping current of the H-bridge; both VREF pins must be connected together.
19 TOFF input Four-level pin that sets the decay-mode off time during current chopping (7, 16, 24 or 32µs) and the ripple current in smart tune ripple control.
20 NC unconnected No connection.
21 DECAY input Four-level decay mode setting pin (smart tune dynamic decay, smart tune ripple control, mixed decay 30% fast, or fast decay).
22 NC unconnected No connection.
23 NC unconnected No connection.
24 IN2 input PWM input that logically controls the state of the H-bridge, with internal pulldown.
25 IN1 input PWM input that logically controls the state of the H-bridge, with internal pulldown.
26 nSLEEP input Sleep mode input: logic high enables the device, logic low enters low-power sleep mode, with internal pulldown; must not be tied to DVDD.
27 CPL passive Charge pump switching node; connect an X7R 0.022µF ceramic capacitor rated for VM between CPH and CPL.
28 CPH passive Charge pump switching node; connect an X7R 0.022µF ceramic capacitor rated for VM between CPH and CPL.
29 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28
Category Power Supply Chip
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VM operating supply voltage VVM 4.5 48 V 7
Logic input voltage VI 0 5.5 V 7
VREF RMS voltage range VREF 0.05 5 V 7
Applied PWM frequency ƒPWM 0 100 kHz PH, EN, IN1, IN2 7
Peak output current IFS 0 6.4 A 7
Operating ambient temperature TA -40 125 °C 7
Operating junction temperature TJ -40 150 °C 7
Junction-to-ambient thermal resistance RθJA 29.7 °C/W PWP (HTSSOP) 28-pin 7
Junction-to-case (top) thermal resistance RθJC(top) 23 °C/W PWP (HTSSOP) 28-pin 7
Junction-to-board thermal resistance RθJB 9.3 °C/W PWP (HTSSOP) 28-pin 7
Junction-to-top characterization parameter ψJT 0.3 °C/W PWP (HTSSOP) 28-pin 7
Junction-to-board characterization parameter ψJB 9.2 °C/W PWP (HTSSOP) 28-pin 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.4 °C/W PWP (HTSSOP) 28-pin 7
VM operating supply current IVM 4 5.5 mA nSLEEP = 1, no motor load 8
VM sleep mode supply current IVMQ 2 4 μA nSLEEP = 0 8
Sleep time tSLEEP 120 μs nSLEEP = 0 to sleep mode 8
nSLEEP reset pulse tRESET 20 40 μs nSLEEP low to clear fault 8
Wake-up time tWAKE 0.8 1.2 ms nSLEEP = 1 to output transition 8
Turn-on time tON 0.8 1.2 ms VM > UVLO to output transition 8
Internal regulator voltage VDVDD 4.75 5 5.25 V No external load, 6V < VVM < 48V 8
Internal regulator voltage (low VM) VDVDD 4.2 4.35 V No external load, VVM = 4.5V 8
Input logic low voltage VIL 0 0.6 V 8
Input logic high voltage VIH 1.5 5.5 V 8
Input logic low current IIL -1 1 μA VIN = 0V 8
Input logic high current IIH 100 μA VIN = 5V 8
Propagation delay tPD 800 ns PH, EN, INx input to current change 8
Four-level input low voltage VI1 0 0.6 V Tied to GND 8
Four-level input voltage 330kΩ VI2 1 1.25 1.4 V 330kΩ ± 5% to GND 8
Four-level input Hi-Z voltage VI3 1.8 2 2.2 V Hi-Z (>500kΩ to GND) 8
Four-level input logic high voltage VI4 2.7 5.5 V Tied to DVDD 8
nFAULT output logic low voltage VOL 0.5 V IO = 5mA 8
nFAULT output logic high leakage current IOH -1 1 μA 8
High-side FET on resistance RDS(ONH) 82 100 mΩ TJ = 25°C, IO = -1A 8
High-side FET on resistance RDS(ONH) 125 150 mΩ TJ = 125°C, IO = -1A 8
High-side FET on resistance RDS(ONH) 140 175 mΩ TJ = 150°C, IO = -1A 8
Low-side FET on resistance RDS(ONL) 82 100 mΩ TJ = 25°C, IO = 1A 8
Low-side FET on resistance RDS(ONL) 125 150 mΩ TJ = 125°C, IO = 1A 8
Low-side FET on resistance RDS(ONL) 140 175 mΩ TJ = 150°C, IO = 1A 8
VREF leakage current IVREF 8.25 μA VREF = 3.3V 8
ITRIP current accuracy ΔITRIP -12 12 % 0.5A < ITRIP < 1A 9
ITRIP current accuracy ΔITRIP -6 6 % 1A < ITRIP < 2A 9
ITRIP current accuracy ΔITRIP -4 4 % 2A < ITRIP < 5A 9
VM UVLO lockout (falling) VUVLO 4.1 4.25 4.35 V VM falling, UVLO falling 9
VM UVLO lockout (rising) VUVLO 4.2 4.35 4.45 V VM rising, UVLO rising 9
Thermal shutdown temperature TOTSD 150 165 180 °C Die temperature TJ 9
Input logic hysteresis VHYS 150 mV 8
Charge pump switching frequency f(VCP) 360 kHz VVM > UVLO; nSLEEP = 1 8
Output pull-up current IO 10 μA 8
Output slew rate tSR 240 V/µs VM = 24V, IO = 1A, between 10% and 90% 8
PWM off time tOFF 7 μs TOFF = 0 9
PWM off time tOFF 16 μs TOFF = 1 9
PWM off time tOFF 24 μs TOFF = Hi-Z 9
PWM off time tOFF 32 μs TOFF = 330kΩ to GND 9
Undervoltage hysteresis VUVLO,HYS 100 mV Rising to falling threshold 9
Overcurrent protection IOCP 8 A Current through any FET 9
Overcurrent deglitch time tOCP 2 μs 9
Thermal shutdown hysteresis THYS_OTSD 20 °C Die temperature TJ 9

CAD (KiCad official)

  • Symbol: DRV8256PPWPR
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28 (KiCad packages3D, STEP)
  • 3D model files: drv8256ppwpr-etched.step / drv8256ppwpr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); drv8256ppwpr.step / drv8256ppwpr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (46 pp, sha256 955cb1f20856cec4, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF