# DRV8244HQDGQRQ1

**Texas Instruments** · Gate Drive ICs · HTSSOP-28

DRV8244HQDGQRQ1 from Texas Instruments, in a HTSSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SR | input | Device configuration pin for slew rate control of the driver output (6-level setting, latched at power-up or wake-up from sleep). |
| 2 | DIAG | input | Device configuration pin for load type indication and fault reaction configuration. |
| 3 | PH/IN2 | input | Controller input pin for bridge operation (PH or IN2 depending on control mode). |
| 4 | EN/IN1 | input | Controller input pin for bridge operation (EN or IN1 depending on control mode). |
| 5 | DRVOFF | input | Controller input pin for bridge Hi-Z; asserting it high Hi-Zs both half-bridges in the HW variant. |
| 6 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 7 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 8 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 9 | OUT1 | power_out | Half-bridge output 1 connected to the motor or load; must be combined with the other OUT1 pins (3 total) to support device current capability. |
| 10 | OUT1 | power_out | Half-bridge output 1 connected to the motor or load; must be combined with the other OUT1 pins (3 total) to support device current capability. |
| 11 | OUT1 | power_out | Half-bridge output 1 connected to the motor or load; must be combined with the other OUT1 pins (3 total) to support device current capability. |
| 12 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 13 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 14 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 15 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 16 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 17 | GND | power_in | Ground pin; must be combined with the rest of the GND pins (6 total) to support device current capability. |
| 18 | OUT2 | power_out | Half-bridge output 2 connected to the motor or load; must be combined with the other OUT2 pins (3 total) to support device current capability. |
| 19 | OUT2 | power_out | Half-bridge output 2 connected to the motor or load; must be combined with the other OUT2 pins (3 total) to support device current capability. |
| 20 | OUT2 | power_out | Half-bridge output 2 connected to the motor or load; must be combined with the other OUT2 pins (3 total) to support device current capability. |
| 21 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 22 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 23 | VM | power_in | Motor supply voltage pin (4.5 V to 35 V operating); must be combined with the other 5 VM pins (6 total) and bypassed to GND with a 0.1-µF ceramic capacitor and a bulk capacitor. |
| 24 | nSLEEP | input | Controller input pin for SLEEP; must be controlled by the controller in the HW variant even if sleep is not needed. |
| 25 | IPROPI | bidirectional | Driver load current analog feedback output; connect an external resistor to ground to generate a voltage proportional to load current. |
| 26 | nFAULT | output | Open-drain fault indication to the controller. |
| 27 | MODE | input | Device configuration pin for MODE (control mode selection). |
| 28 | ITRIP | input | Device configuration pin for ITRIP level for high-side current limiting. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28 |
| Category | Power Management |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply pin voltage VM | VM | -0.3 |  | 40 | V |  | 12 |
| Power supply transient voltage ramp VM |  |  |  | 2 | V/µs |  | 12 |
| Output pin voltage OUT1, OUT2 |  | -0.9 |  | 0.9 | V | max is VVM + 0.9 V | 12 |
| Driver disable pin voltage DRVOFF |  | -0.3 |  | 40 | V |  | 12 |
| Logic I/O voltage EN/IN1, PH/IN2, nFAULT |  | -0.3 |  | 5.75 | V |  | 12 |
| Configuration pins voltage MODE, ITRIP, SR, DIAG |  | -0.3 |  | 5.75 | V | HW variant | 12 |
| Analog feedback pin voltage IPROPI |  | -0.3 |  | 5.75 | V |  | 12 |
| Sleep pin voltage nSLEEP |  | -0.3 |  | 40 | V |  | 12 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 12 |
| Junction temperature | TJ | -40 |  | 150 | °C |  | 12 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 12 |
| Power supply voltage VM | VVM | 4.5 |  | 35 | V |  | 13 |
| Logic pin voltage | VLOGIC | 0 |  | 5.5 | V | EN/IN1, PH/IN2, nSLEEP, DRVOFF, nFAULT | 13 |
| PWM frequency | fPWM | 0 |  | 25 | KHz | EN/IN1, PH/IN2 | 13 |
| Configuration pin voltage | VCONFIG | 0 |  | 5.5 | V | HW variant, MODE, ITRIP, SR, DIAG | 13 |
| Analog feedback voltage IPROPI | VIPROPI | 0 |  | 5.5 | V |  | 13 |
| Operating ambient temperature | TA | -40 |  | 125 | °C |  | 13 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 13 |
| VM current in SLEEP state (25°C) | IVMQ |  |  | 1 | µA | VVM = 13.5 V, VnSLEEP = 0 V or VVDD < PORVDD_FALL, TA = 25°C | 13 |
| VM current in SLEEP state (125°C) | IVMQ |  |  | 9.2 | µA | VVM = 13.5 V, VnSLEEP = 0 V or VVDD < PORVDD_FALL, TA = 125°C | 13 |
| VM current in STANDBY state | IVMS |  | 3 | 5 | mA | VVM = 13.5 V | 13 |
| RESET pulse filter time | tRESET | 5 |  | 20 | µs | Reset signal on nSLEEP pin for HW (H) variant | 13 |
| SLEEP command filter time | tSLEEP | 40 |  | 120 | µs | Sleep signal on nSLEEP pin for HW (H) variant | 13 |
| Wake-up command filter time | tWAKEUP |  |  | 10 | µs | Wake-up signal on nSLEEP pin for HW (H) and SPI (S) variants | 14 |
| Time for communication available after wake-up or power-up | tCOM |  |  | 400 | µs | Wake-up signal on nSLEEP pin or power cycle - VVM > VMPOR_RISE or VVDD > VDDPOR_RISE | 14 |
| Time for driver ready after wake-up or power-up | tREADY |  |  | 1 | ms | Wake-up signal on nSLEEP pin or power cycle - VVM > VMPOR_RISE or VVDD > VDDPOR_RISE | 14 |
| Input logic low voltage nSLEEP | VIL_nSLEEP |  |  | 0.65 | V | nSLEEP pin | 14 |
| Input logic high voltage nSLEEP | VIH_nSLEEP |  |  | 1.55 | V | nSLEEP pin | 14 |
| Input logic low voltage | VIL |  |  | 0.7 | V | DRVOFF, EN/IN1, PH/IN2 pins | 14 |
| Input logic high voltage | VIH |  |  | 1.5 | V | DRVOFF, EN/IN1, PH/IN2 pins | 14 |
| Internal pull-down resistance on nSLEEP | RPD_nSLEEP | 100 |  | 400 | KΩ | Measured at min VIL level | 14 |
| Internal pull-up resistance on DRVOFF | RPU | 200 |  | 550 | KΩ | Measured at min VIH level | 14 |
| Internal pull-down resistance on EN/IN1 and PH/IN2 | RPD | 200 |  | 500 | KΩ | Measured at max VIL level | 14 |
| Sink current on nFAULT when asserted low | InFAULT_PD | 5 |  |  | mA | VnFAULT = 0.3 V | 14 |
| Supply pin voltage during reverse current | VVM_REV |  | 1.4 |  | V | IVM = - 5 A, device in unpowered state | 13 |
| Input hysteresis nSLEEP | VIHYS_nSLEEP |  | 200 |  | mV | nSLEEP pin | 14 |
| Input hysteresis | VIHYS |  | 100 |  | mV | DRVOFF, EN/IN1, PH/IN2 pins | 14 |
| Junction-to-ambient thermal resistance | RθJA |  | 30.1 |  | °C/W | HVSSOP package | 13 |
| Junction-to-case(top) thermal resistance | RθJC(top) |  | 27.2 |  | °C/W | HVSSOP package | 13 |
| Junction-to-board thermal resistance | RθJB |  | 8.8 |  | °C/W | HVSSOP package | 13 |
| Junction-to-top characterization parameter | ΨJT |  | 1.2 |  | °C/W | HVSSOP package | 13 |
| Junction-to-board characterization parameter | ΨJB |  | 8.8 |  | °C/W | HVSSOP package | 13 |
| Junction-to-case(bottom) thermal resistance | RθJC(bot) |  | 1 |  | °C/W | HVSSOP package | 13 |

## CAD (KiCad official)

- Symbol: `DRV8244HQDGQRQ1`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28 (KiCad packages3D, STEP)
- 3D model files: `drv8244hqdgqrq1-etched.step` / `drv8244hqdgqrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `drv8244hqdgqrq1.step` / `drv8244hqdgqrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/drv8244-q1.pdf) (80 pp, sha256 `98b59e9ddf91f007`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/drv8244hqdgqrq1-datasheet.pdf)